Block Diagram (1/2) - Sony DP-IF8000 Service Manual

DP-IF8000
Q Q
3 7 6 3 1 5 1 5 0

6-2. BLOCK DIAGRAM (1/2)

IC1
DIGITAL
3 DIN0
IN-1
OPTICAL
IC2
DIGITAL
4 DIN1
IN-2
OPTICAL
1 48 34 24 23 26 27 28
IC3
LINE AMP
J101
L 3 1
LINE
IN
R 5 7
Q101 Q102
T E
L 1 3 9 4 2 2 9 6 5 1 3
UCON
VDD
S101
ATT
0dB -8dB
IC206
D201-221
LED DATA DECODER,
DISPLAY
LED DRIVER
OUT14
I
OUT0
SDO0
2
SERIAL-IN
SCK0
3
CLOCK
XLATCH 4
LED DRIVER
OUT15 XENABLE 21
20
Q201,202
VDD
24
w w w
SW1
POWER
SW2
REG
INPUT
9V
SW3
EFFECT
SW4
OUTPUT
IC4
DIR
16 7
DATAO
6
17 16 15 14 13 22 15 14 13 36 35 37 38
7 3 2
14 AIN_L
SDOUT 4
AIN_R
13
16
IC20
ADC
47 46 91 61 1 2 3 4 5 6 7 8
83 P101
82 P100
73
P60
x a o
IC17
74
P61
. i
RESET
15 1 RESET
75 P62
76 P63
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IC11
DECODER
IC8
SELECT SWITCH
1 10 SDO4
5
IC13-IC15
RAM
WE 12 67
WR
OE 28 68 RD
CS
5 51 AA2
A0 A0
16
I I
A16 A16
I/O0 D0
8
I I
I/O7 D7
IC13
I/O0
D8
8
I
I
I/O7
D15
IC14
Q Q
3 7
I/O0
D16
8
I
I
I/O7
D23
IC15
144 143 1 2
X3
8MHz
92 10 11
IC18(1/2)
SYSYTEM
CONTROL
u 1 6 3
y
D17
< UCON1
3
VDD
D18
18 18
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2 4
8 9 9
IC19
MAIN DSP
FLRSG
SDO0 4 11 SDO5
SLRSG
SDO1 5 10 SDO4
CLFSG
6 7
SDO2 SDO3
OTHSG
SDO3 7 48
SDO5_1/SDIO_1
SDO4_1/RDI1_1
DSPEFF
41
P82
DSPTMP1
40 PB3
DSPTMP2
37
FB4
DSPTMP3
36 FB5
DSPTMP4
35
FB6
DSPTMP5
34 FB7
MCK
55 EXTAL
60 SCKR_1
53 SCKT_1
MCK
EXTAL 55 15 SCKR
BCK
SCKR 15 14 SCKT
BCK
14 59 FSR_1
SCKT
FSR 13 50 FST_1
6 3 1 5 1 5 0 8 9
LRCK
LRCK
FST 12 13 FSR
4 44 143 1 2 3
21 56 57 58 59 51 52 53 54 55 50
m
• Signal Path
c o
:LINE(ANALOG)
.
:LINE(DIGITAL)
2
8 9 9
SDO0 4 VPOUT1
SDO2 6 RCS
SDO1 5
RINFO TX MAIN
A
SECTION (2/2)
FST 12 DILRCK
138 VPOUT2
2 4 9 8 2 9 9
44 42 43
TX MAIN
CONTROL B
SECTION (2/2)
BUS
60 49 48