Table of Contents
Advertisement
A
B
SCHEMATIC DIAGRAM (VIDEO 1/3)
1
from VIDEO (3)
Page 108
J6
2
C-INPUT SELECTOR
3
4
Y-INPUT SELECTOR
C-REC OUT SELECTOR
5
Y-REC OUT SELECTOR
6
0.8
7
8
9
C
D
E
to VIDEO (2)
Page 107
from MAIN (3)
Page 111
D1
D2
5.0
16
0
14
6
-5.0
-5.0
9
0
13
3
0
0
0
5
4
0
0
14
0
0
0
3
0
15
5.0
0
12
0
1
0
0
5
-5.0
0
3
0
0
4
5.0
13
1.4
0
14
1.4
13
3
2.5
12
0
0
2.5
1.2
0
14
0
15
0
12
0
0
1
0
1
-5.0
0
5
0
2
15
0
0
0
3
0
1
0
4
0
2
15
0
0
13
14
0
0
1
15
-0.1
0
13
3
0
14
0
0
2
3
0
14
4.9
0
4
0
15
13
-0.1
0
0
12
0
5
12
-5.0
4.9
0
1
0
7
0
0
5
11
-0.1
0
8
10
0
3
4.9
0
4
0
1
0
13
3
0
15
-0.1
0
14
0
2
3
15
5
4
0
0
0
4.9
0
4
0
12
0
3
13
-0.1
0
0
5
0
1
12
-5.0
4.9
0
5
0
7
0
11
-0.1
0
3
0
8
10
0
4
4.9
4.9
4.9
1.4
0.8
0
4.9
-0.6
1.4
1.4
1.4
4.9
0
-0.6
1.4
4.9
1.4
0
1.4
0.7
2.1
0
IC1, 10, 11: LA7108M
Video Amp
IC4~7: TC74HC4051AP
Analog Multiplexer/Demultiplexer
INHIBIT
VDD
VIN1+
1
16
+VCC
6
16
NFB1
2
VOUT1
6dB
DR
15
A
11
LEVEL
B
10
CONVERTER
C
9
MUTE1
3
14
GND
VSS
8
VEE
7
VIN2+
VOUT2
4
13
X0
13
6dB
DR
X1
14
NFB2
5
12
MUTE2
X2
15
X3
12
-VCC1
6
11
VOUT3
X4
1
X5
5
7
VIN3+
6dB
DR
10
MUTE3
X6
2
X7
4
NFB3
8
9
-VCC2
F
G
to SUB TRANS (3)
Page 110
K1
to SUB TRANS (7)
Page 109
from FUNCTION (1)
B8
0
7
11
0
0
8
10
4.2
4.9
4.9
4.9
0
4.9
0
-5.0
4.9
4.6
0
0
4.5
14
1
2
2.6
2.6
2.6
4.9
4.9
4.5
0
4.3
4.9
0
4.5
0
-5.0
4.5
0
0
0
13
0
0
4.9
0
0
4.9
4.9
4.9
4.3
0
4.9
1.6
0
4.3
-0.6
-0.1
-5.0
0
1.6
-0.6
-5.0
-0.6
-1.3
-0.6
4.9
4.9
0
4.9
-5.0
0
0
-5.0
ON
SCREEN
7
2.1
4.9
4.9
IC8, 9: TC74HC4053AP
Analog Multiplexer/Demultiplexer
INHIBIT
VDD
6
16
A
11
BINARY TO 1-OF-8
INPUT STATES
LEVEL
DECODER WITH INHIBIT
"ON" CHANNEL (S)
B
10
CONVERTER
INHIBIT
C
B
A
C
9
0
0
0
0
0
VSS
8
0
0
0
1
1
SW
VEE
7
0
0
0
1
2
SW
0X
12
0
0
1
1
3
SW
1X
13
0
1
0
0
4
X
0Y
2
SW
3
0
1
0
1
5
1
1
0
6
1Y
SW
0
1
0
1
1
1
7
0Z
5
SW
1
X
X
X
NONE
1Z
3
SW
SW
H
I
# All voltages are measured with a 10MΩ/V DC electric volt meter.
# Components having special characteristics are marked s and must be replaced
Page 104
with parts having specifications equal to those originally installed.
I5
# Schematic diagram is subject to change without notice.
x: NOT USED
O: USED / APPLICABLE
4.7
4.3
3
4
5
6
2.6
2.6
4.3
4.5
12
10
8
4.9
0
11
9
4.9
4.5
7
0
0
4.4
4.9
14
10
0.4
11
9
8
4.9
0
1.2
-0.6
4
5
3
6
0
4.9
0
7
0
Point 7 Pin 16 of IC12
0
-0.6
0
1
2
4.9
4.3
0
13
12
4.9
IC13, 14: TC74HCU04AP
Hex Inverters
1A
1
INPUT STATES
1Y
2
"ON" CHANNNEL (S)
BINARY TO 1-OF-8
INHIBIT
C
B
A
DECODER WITH INHIBIT
2A
3
0
0
0
0
0X, 0Y, 0Z
0
0
0
1
1X, 0Y, 0Z
2Y
4
0
0
1
0
0X, 1Y, 0Z
0
0
1
1
1X, 1Y, 0Z
3A
5
SW
14
X-COM
0
1
0
0
0X, 0Y, 1Z
SW
0
1
0
1
1X, 0Y, 1Z
3Y
6
SW
0
1
1
0
0X, 1Y, 1Z
15
Y-COM
SW
0
1
1
1
1X, 1Y, 1Z
GND
7
1
X
X
X
NONE
SW
4
Z-COM
SW
J
K
L
RX-Z1/DSP-AZ1
IC15: BU2092
Serial In/Parallel Out Driver
Vss
1
18
VDD
14
VCC
DATA
OE
2
17
13
6A
CLOCK
3
Control
16
Q11
Circuit
LCK
4
15
Q10
12
6Y
Q0
5
14
Q9
Q1
6
13
Q8
11
5A
Q2
7
12
Q7
10
5Y
Q3
8
11
Q6
Q4
Q5
9
10
9
4A
8
4Y
106
Hide quick links:
Advertisement
Table of Contents
