Spectra MB720 User Manual page 43

AGP Fast Write
This accelerates memory write transactions from the chipset to the AGP
device.
AGP Master 1 WS Write
When enabled, this changes the default from a 2ws to a 1ws which
will increase AGP Writing.
AGP Master 1 WS Read
By default, the AGP busmastering device waits for at least 2 wait states
before it starts a write transaction. When enable, this option sets the delay
to 1 wait state.
AGP 3.0 Calibration cycle
By default, this field is disabled.
VGA Share memory Size
By default, this field is set to 64M.
Direct Frame Buffer
By default, this field is Enabled.
Select Display Device
By default, this field is set to CRT.
Panel Type
By default, this field is set to 02.
TV H/W Layout
By default, this field is set to Default.
HDTV Type
By default, this field is set to HDTV 720P.
TV Encoder Input
By default, this field is set to RGB Input.
TV Type
By default, this field is set to NTSC.
TV Output AUTO Detect
By default, this field is set to Disabled.
TV Output Connector
The field allows you to choose the TV output connector to be used.
Anti-Dot Crawl
By default, this field is set to Disabled.
CPU & PCI Bus Control
The fields related to CPU & PCI Bus Control are listed below.
PCI Master 0 WS Write
This determines whether the chipset inserts a delay before any writes from
the PCI bus.
PCI Delay Transaction
This is used to meet the latency of PCI cycles to and from the ISA bus.
Vlink mode selection
The default is set to Mode 1.
Vlink 8X Support
By default, this field is enabled.
MB720 User's Manual
BIOS SETUP
39