Description Of Major Ics - JVC UX-M55 Service Manual

Description of major ICs

TC9462F (IC701) : Digital servo single chip processor
1. Terminal layout
80 51
1 30
2. Pin function
Pin No. Symbol
1 TEST0
2 HSO
3 UHSO
4 EMPH
5 LRCK
6 V
SS
7 BCK
8 AOUT
9 DOUT
10 MBOV
11 IPF
12 SBOK
13 CLCK
14 V
DD
15 V
SS
16 DATA
17 SFSY
18 SBSY
19 SPCK
20 SPDA
21 COFS
22 MONIT
23 V
DD
24 TESIO0
25 P2Vref
26 HSSW
27 ZDET
28 PDO
I/O
I Test mode terminal. Normally, keep at open.
O Playback speed mode flag output terminal. (Not connect)
O
UHSO HSO
H H
H L
L H
L L
O Subcode Q data emphasis flag output terminal. Emphasis ON at "H" level and
OFF at "L" level. The output polarity can invert by command. (Not connect)
O Channel clock output terminal. (44.1kHz) L-ch at "L" level and R-ch at "H" level.
The output polarity can invert by command. (Not connect)
- Digital ground terminal.
O Bit clock output terminal. (1.4112MHz) (Not connect)
O Audio data output terminal. (Not connect)
O Digital data output terminal. (Not connect)
O Buffer memory over signal output terminal. Over at "H" level. (Not connect)
O Correction flag output terminal. At "H" level, AOUT output is made to correction
impossibility by C correction processing. (Not connect)
2
O Subcode Q data CRCC check adjusting result output terminal. The adjusting
result is OK at "H" level. (Not connect)
I/O Subcode P W data readout clock input/output terminal. This terminal can select
by command bit. (Not connect)
- Digital power supply voltage terminal.
- Digital ground terminal.
O Subcode P W data output terminal. (Not connect)
O Playback frame sync signal output terminal. (Not connect)
O Subcode block sync signal output terminal. (Not connect)
O Processor status signal readout clock output terminal. (Not connect)
O Processor status signal output terminal. (Not connect)
O Correction frame clock output terminal. (7.35kHz) (Not connect)
O Internal signal (DSP internal flag and PLL clock) output terminal. Selected by
command. This terminal output the text data with serial by command. (NC)
- Digital power supply voltage terminal.
I Test input/output terminal. Normally, keep at "L" level. The terminal that inputted
the clock for read of text data by command.
- PLL double reference voltage supply terminal.
O 2/4 times speed at "VREF" voltage. (Not connect)
O 1 bit DA converter zero detect flag output terminal.
O Phase difference signal output terminal of EFM signal and PLCK signal.
Function
PLAYBACK SPEED
Normal
2 times
4 times
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UX-M55
1-21