Block (1 Of 8) Diagram - Panasonic TH-103PF12U Service Manual

TH-103PF12U

11.4. Block (1 of 8) Diagram

HHH
HDMI INTERFACE
H6 H5
HDMI IN A HDMI IN B
IC3324
EEPROM
EDID A
For HD
IC3325
EEPROM
EDID A
For FHD
IC3302
EEPROM
EDID B
For HD
IC3301
EEPROM
EDID B
For FHD
IC3304
3.3V
->5V
IC3303
3.3V
->5V
DDC0_IIC
DDC1_IIC
DECODE
IIC
HDMI_IIC
H/V
HA
COMPONENT VIDEO TERMINAL
JK3001
COMPONENT
VIDEO IN
Q3302
JK3002
Q3303
AUDIO IN
IC3002
EEPROM
+5V
IC3328
IC3335
BUFFER
BUFFER
IC3326
IC3334
BUFFER
BUFFER
IC3330
BUFFER
PLAG_DET
+3.3VREG
+3.3V
IC3307
+1.8V +1.8V
HDMI I/F RECEIVER
10bit A/D
IC3308
HDMI PROCESSOR
HDMI_SD
AUDIO
HDMI
INTERFACE
VIDEO
INTERFACE
HDCP KEY
Y0,Y1,UV0,UV1
Y2-Y9 UV2-UV9
A/D CONV. SW
IVDO
IIC
IC3321
IC3310
HDMI_IIC
EXPAND I/O
+5VSTB MAIN MICOM
EX_RESERVE1
P1 ADIN2
EX_RESERVE2
P2 ADIN3
SLOT_IIC2
IIC EX_RESERVE3
P3
ADIN4
H1 DS13
A38 Y/G
A36 PB/B
PR/R
A34
A26
AUDIO L
AUDIO R
A28
SLOT+9V A21 SLOT9V
STB5V
A22 STB5V
IIC_DATA3
B24 IIC_DATA3
IIC_CLOCK3
B25
IIC_CLOCK3
IC3339
+3.3VREG
+3.3V
IC3338
IC3319
CONFIG
+5V
ROM
IIC SLOT_IIC2
+3.3VREG
IC3329
IC3322
IC3306
BUFFER
AUDIO AMP L
AUDIO DAC
+5V
L
VDD
AOUTR
R
BICK
AOUTL
IC3323
AUDIO AMP R
+3.3VREG
IC3344
+2.5V +2.5V
IC3342
+1.2V +1.2V
Y0,Y1,UV0,UV1
Y0,Y1,UV0,UV1
Y2-Y9 UV2-UV9
Y2-Y9
UV2-UV9
RESERVE1 CONTROL BUS RESERVE1
RESERVE6
RESERVE6
HD/FHD HD/FHD
HDMI_5V_DET1
HDMI_5V_DET1
HDMI_5V_DET2
HDMI_5V_DET2
HDMI_5V_DET1
HDMI_5V_DET2
NRST nCONFIG
+3.3VREG
IC3312
RESET
62
H1 DS12
B38 SLOT15V
+5VSTB
B37 SLOT15V
A22 STB5V
+9V
A21 SLOT9V
SLOT9V
+5V B21
A19 SLOT5V
B19 SLOT5V
B39 PLUG DET
A23 HD/FHD DET
B25 SLOT_SCL
SLOT_IIC2
B24 SLOT_SDA
L_OUT+
A26 HDMI_L
R_OUT+
A28 HDMI_R
IC3341
A2 LVDS_TX0+-
FPGA
|
|
LVDS DATA
LVDS_TX9+-
B15
LVDS_TXC+-
+3.3VREG
VCC
DCLK DCLK
IC3314
ASDO ASDO
DATAO DATAO CONFIG ROM
nCSO nCSO (FPGA)
O_CLK FIN
IC3343
S0-3 S0-3
CLK1 FOUT
CPG
CLK4 FOR
H2 FACTORY
USE
FOR
H3 FACTORY
USE