Changhong Electric PT4206 Service Manual page 20

Pin Function Descriptions
Pin(s)
90 RX0+
91 RX0-
85 RX1+
86 RX1-
80 RX2+
81 RX2-
93 RXC+
94 RXC-
49 56 QO0 QO7
59 66 QO8 QO15
69 75,77 QO16 QO23
10 17 QE0 QE7
20 27 QE8 QE15
30 37 QE16 QE23
99 RESERVED
100 OCK_INV
1 HS_DJTR
2 PD
3 ST
4 PIXS
7 STAG_OUT
8 SCDT
9 PDO
44 ODCK
46 DE
47 VSYNC
48 HSYNC
18,29,43,57,78 OVCC
19,28,45,58,76 OGND
6,38,67 CVCC
5,39,68 GND
82,84,88,95 DAVCC
Name
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input clock pair.
TMDS Low Voltage Differential Signal input clock pair.
8bit odd-pixel Blue output
8bit even-pixel Green output
8bit odd-pixel Red output
8bit even -pixel Blue output
8bit even -pixel Green output
8bit even -pixel Red output
Must be tied HIGH for normal operation.
ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.
This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To
Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.
Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.
Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.
Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.
A LOW level selects staggered output drive.
Sync Detect. A HIGH level is outputted when DE is
actively toggling indicating that the link is alive. A
LOW level is outputted when DE is inactive, indicating
the link is down.
Output Driver Power Down (active LOW). A HIGH
level indicates normal operation. A LOW level puts all
the output drivers only (except SCDT and CTL1) into
a high impedance (tri-state) mode.
Output Data Clock. This output can be inverted using
the OCK_INV pin.
Output Data Enable.
Vertical Sync input control signal.
Horizontal Sync input control signal.
Output VCC
Output GND
Digital Core VCC,
Digital Core GND.
Analog VCC
Function
20