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LG CRD-8483B Service Manual page 21

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Pin No.
Symbol
98
VPVSS
Host Interface
99
DEVSEL
DASP_
100
CS3FX_
101
102
CS1FX_
103
DGND
104,105,107
DA[2:0]
PDIAG_
106
108
DVDD
109
IOCS16_
110
INTRQ
111
DMACK_
112
IORDY
113
DOIR_
114
DIOW_
Type
Description
Ground
Ground pin for varipitch VCO circuitry.
TTL Input
Device Select. Cleared to zero indicates the MT1198 is master device.
50K pull_up
Set to one indicates the MT1198 is slave device.
TTL I/O
Device Active/Device 1 Present. This is a time-multiplexed signal which
50K pull_up
indicates that a device is active, or that Device 1 is present. A 10K-ohm
pull-up resistor shall be connected to this signal externally.
TTL Input, SMT
Device Chip Select 1. This is the chip select signal from the host to select
50K pull_up
the Control Block Registers.
TTL Input, SMT
Device Chip Select 0. This is the chip select signal from the host to select
50K pull_up
the Command Block Registers.
Ground
Ground pin for internal digital circuitry.
TTL Input, SMT
Device Address. This is the 3-bit binary coded address provided by the
50K pull_up
host to access an ATA register or data.
TTL Input,
Passed Diagnostics. This signal is asserted by Device 1 to indicate to
50K pull_up
Device 0 that it has completed diagnostics.
Power(5V)
Power pin for internal digital circuitry.
TTL Output,
Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16_indicates
Open drain
to the host system that the 16-bit data port has been addressed and that
the device is prepared to send or receive a 16-bit data word. The MT1198
will always assert IOCS16_ when the host reads the ATAPI Data
Register.
Device interrupt. This signal is used to interrupt the host system. INTRQ
TTL I/O
Slew rate
is driven only when the MT1198 is addressed, i.e.,
DRV1 01h.RW7 =DRV 16h.RW4 . When not driven, INTRQ is in a high
impedance state.
DMA Acknowledge. This signal shall be used by the host in response to
TTl Input, SMT
DMARQ to acknowledge that it is ready for DMA transfers.
50K pull_up
TTL Output
I/O Channel Ready. This signal is negated (pulled low) during PIO to
extend the host transfer cycle of any host register access (Read or Write)
Slew rate
when the MT1198 is not ready to respond to a data transfer request.
When IORDY is not negated, it is in a high impedance state. In Ultra
DMA transfers, the signal becomes either DDMARDY_(Device Ultra
DMA Ready) that is asserted by the MT1198 to indicate to the host that it
is ready to receive data, or DSTROBE (Device Ultra DMA Data Strobe)
whose rising edge and falling edge latch the data from DD0-DD15 into
the host.
Device I/O Read. This is the ATA read strobe signal. In PIO or multiword-
TTL Input, SMT
DMA the falling edge of DIOR_ enables data from the MT1198 onto the
50K pull_up
host data bus, DD0-DD7 or DD0-DD15. The rising edge of DIOR_ then
latches the data at the host. During Ultra DMA transfers the signal
becomed either HDMARDY_ (Host Ultra DMA Ready), which is asserted
by the host to indicate to the MT1198 that host is ready to receive data,
or HSTROBE (Host Ultra DMA Data Strobe), whose rising edge and
falling edge latch the data from DD0-DD15 into the MT1198.
Device I/O Write. This is the ATA write strobe signal. In PIO or multiword-
TTL Input, SMT
DMA the rising edge of DIOW_ latches data from the host data bus,
50K pull_up
DD0-DD7 or DD0-DD15, into the ATA registers or the ATAPI Packet FIFO
of the MT1198. In Ultra DMA transfers the signal becomes STOP (Stop
Ultra DMA Data Transfer), which is negated by the host before data can
be transferred by an Ultra DMA burst, and asserted by the host when it
want to terminate an Ultra DMA burst.
19

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