LG CRD-8483B Service Manual page 20

Pin No. Symbol
X'tal Interface
54 XTALI
XTALO
55
DRAM Interface
DVDD
56
57 DGND
58, 60, 62, RD[15:8]/
VIO[15:8]
65, 67, 69,
71, 73
59, 61, 63, 66, RD[7:0]
68, 70, 72, 74
64 DVDD3
75 CASL_/
CAS_
76 CASH_/
RWEH_
77 RWE_/
RWEL_
78 RAS_
79
DVDD
80-88
RA[8:0]
89 DGND
Audio Interface
90
ADGO/
VIO0
Internal Audio Interface
DACVSS
91
RO
92
DACVREF
93
LO
94
DACVDD
95
Varipitch VCO Interface
VPVDD
96
VCOCIN
97
18
Type Description
Input X'tal input. The working frequency is 33.8688 MHz.
Output X'tal output.
Power(5V) Power pin for internal digital circuitry.
Ground Ground pin for internal digital circuitry.
TTL I/O, Slew rate Buffer RAM Data/Versatile Input/ Output. These pins are the bi-directional upper
50K pull_up Buffer RAM data bus to the external buffer memory. When an 8-bit DRAM is
used, the RD8-RD15 signals becomes Versatile I/O pins, VIO8-VIO15.
TTL I/O, Slew rate Bi-directional lower Buffer RAM data bus.
50K pull_up
Power(3.3V) Power pin for internal digital circuitry.
TTL Output Column Address Strobe Low/Column Address Strobe. When
Slew rate TWE63h.RW6 is 0, this pin is the Column Address Strobe Low signal for
accessing the lower bytes of a two-CAS_ 16-bit DRAM. When
TWE63h.RW6 is 1 or when an 8-bit DRAM is used, this pin shall be
connected to CAS_ of the DRAM.
TTL Output Column Address Strobe High/RAM Write Enable High. When a 16-bit
Slew rate DRAM is used, this pin functions as Column address Strobe High for
accessing the upper bytes of a two-CAS_DRAM if TWE63h.RW6 is 0, or
as Write Enable High for writing the upper bytes of a two-WE_DRAM.
TTL Output RAM Write Enable/RAM Write Enable Low. When TWE63h.RW6 is 0 or
when an 8-bit DRAM is used, this pin is the active-low write strobe to the
external buffer DRAM. When TWE63h.RW6 is 1, this pin is the Write
Enable Low signal for writing the lower bytes of a two-WE_16-bit DRAM.
TTL Output
Row Address Strobe.
Slew rate
This output is the Row Address Strobe signal to the buffer DRAM.
Power(5V)
Power pin for internal digital circuitry.
TTL I/O, Slew rate
Buffer RAM Address.
50K pull_down These pins are the address bus to the external buffer DRAM.
Ground
Ground pin for internal digital circuitry.
TTL I/O, Slew rate
Digital Audio Output/Versatile I/O 0. The signal is either the Digital Audio
SMT, 50K pull_up Output which supplies the IEC-958 digital audio data when
A0SEL00h.RW7=1 and ADOE2Eh.RW0=1, or the Versatile I/O 0 pin
otherwise.
Ground
Ground pin for internal DAC circuitry.
Analog Output
Right channel of audio.
Analog Output
Reference voltage for external audio filter circuit.
Analog Output
Left channel of audio.
Analog Power(5V)
Power pin for internal DAC circuitry.
Analog Power(5V)
Power pin for varipitch VCO circuitry.
Analog Input
Connect capacitor for compensator loop filter.