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LG CRD-8483B Service Manual page 18

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• IC501 (MT1198CE) : DSP+ATAPI DECODER+µ-COM
Block Diagram
VBDPLL
PLLVSS
LPIO
LPIN
Data Slicer
LPFO
and Data PLL
LPFN
IREF
PDO
PLLVDD
UP3_5/UT1
UP3_4/UT0
DGND
UP3_2/UINT0
UP3_1/UTXD
UP3_0/URXD
DVDD
IO5
IO6
IO7
Interface
IO8
LED
Control
EJECT_
PLAY_
UP1_0/UA16
UP2_7/UA15
UP3_6/UWR_
UP2_6/UA14
UP2_5/UA13
UP2_4/UA12
UP2_3/UA11
UP2_1/UA9
UPSEN_/O9
UP2_0/UA8
DGND
UP2_2/UA10
UALE/IO10
IO4/CS_
UP0_7/UAD7
UP0_6/UAD6
UP0_5/UAD5
UP0_4/UAD4
UP0_3/UAD3
UP0_2/UAD2
UP0_1/UAD1
16
RFRP
Servo
Circuit
ADC
CLV & Zone-
CLV & True-
Sync
CAV Control
Protection
Mega
CIRC Error
EFM & Q-code
and
Correction
Demodulation
GPIO
Subcode
FIFO/
Parallelizer
8032
Micro processor
GPIO
X'tal Clock
Control
Generator
PDM &
PWM
DAC
Servo
DSP
Audio
Processing
Unit
Audio
Playback
Logic
Buffer Memory Controller
Mega interface
and GPIO Control
Reset
Circuitry
1PLL
Decoder & UP
Clock Generator
RSPC
Host
Decoding
Data FIFO
Logic
DSP Data
FIFO/
Parallelizer
Host
Interface
Logic
Descrambler
RSPC
Sync
Detector
ATAPI
Packet
FIFO
Varipitch
Digital Emphasis
Clock
Generator
Over-sampling
DAC &
Digital Filter
DDS
DD6
DVDD
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DGND
DD2
DD13
DD1
DD14
DD0
DD15
DMARQ_
DIOW_
DIOR_
IORDY
DMACK_
INTRQ
IOCS16_
DVDD
DA1
PDIAG_
DA0
DA2
DGND
CSIFX_
CS3FX_
DASP_
DEVSEL
VPVSS
VCOCIN
VPVDD
DACVDD
LO
DACVREF
LPF
RO
DACVSS
ADGO/VIO0
DGND

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