Sanyo DC-F430AV Service Manual page 35

No. Pin Name VO
1 SCOR
0 Turns [H] when sync SO or SI is detected.
2 S B S O
0 Serial output of sub-code P - W.
3 E X C K
Clock input for reading SBSO.
4
0 Serial output of SUBQ (80-bit).
5 S O C K
Clock input for reading SQSO.
6 M U T E
7 S E N S
0 SENS signal output to CPU.
8 X R S T
System reset, [L] at resetting.
9 D A T A
lnouts serial data from CPU.
Latches input from CPU. Serial date latches at
1 0 I
falling edge.
1 1 C L O K
Inputs serial data transfer clock from CPU.
1 2 v s s
SENS sional
1 4
0 Inputs track jump count signal.
15 D A T O
Outputs serial data to SSP.
Outputs latches to SSP. Serial data latches at
16 X L T O
falling edge.
17
C L K O Outputs serial data transfer clock to SSP.
S P O A Interface for extension of M. processor (input A).
1 9 SF'OB Interface for extension of M. processor (input B).
X L O N 0
Focus OK si nal in ut pin. Used servo auto
FOK I
sequencer wit! SEN4 output.
24 MON
0 ON/OFF control signal for spindle motor.
MDP
0 Servo control sianal for soindle motor.
M D S
0 Servo control signal for spindle motor.
T
27 L O C K
GFS sianal turns out 111 8 or more times in
T E S T
Pin for TEST. Normal used stage : GND.
lnouts to filter for master PLL.
of charge pump for master PLL.
VDD supply for digital. (+5V)
33 AVSE
supply for analq. (OV)
I l IVCO control voltaae inout
3 5
Power supply for analog. (+5V)
36 RF
EFM signal input.
I n p u t s ccnstant
37 BIAS I
correction circuit.
Inputs comparator
33 A S Y O
0 EFM fill swing outpuf. ([L] = VSS, [H] = VDD)
[L] : OFF d asymmetly correction. [H] : ON of
.
An
ASYF
Function
from SSP.
for extensionof M. processor (input c).I
for extensionof M. processor (output). I
h
for master PLL.
c u r r e n t f o r a s y m m e t r y
voltage for asymmetry
correction.
D/A interface for 48-bit slot. Ward clock (f =
D/A interface for 48-bit
lnouts LR clock to DAC. (48-bit
4 4 PCMD
0 D/A interface. Serial data (2'SCOMP,
45
Inputs audio data to DAC. (48-bit
46 B C K
0 D/A
47
Inputs bit clock to DAC. (48-bit
48 G T O P
GTOP signal output.
XUGF
0 XUGF signal output.
50 X P C K
0 XPCK sianal outout.
I 51 1 GFS I 0
5 2 RFCK
0 RFCK signal output.
53 v s s
54
0
I
XROF 0 X R O F signal output.
56 0
0
I I I
58 MNTO 0 IMNTO
I
F S T T 0 divided outout of Dins 73 or 74.
0 4.2336 MHz output.
6 1 DOUT
0 Digital out OUTPUT pin.
E M P H
emphasis or [L] for that without emphasis.
De-emphasis ON/OFF d DAC. [H] at ON, [L] at
63 I
WFCK
0 WFCK(Write Frame Clock) signal output.
Z E R O L
detection for non-sound data (L-ch).
66 ZEROR
detection for non-sound data (R-ch).
67
Test pin for DAC. Normal used state : [L]
68 VDD
NLPWM
0 Outputs PWM for L-ch. (Negative Phase)
70 LPWN
0 Outputs PWM for L-ch. (Positive Phase)
7 1 AVDD2
Power supply for PWM driver.
Power
Inputs X'tal oscillation circuit (33.8688 MHz).
74 X T A O
0 Outputs X'tal oscillation circuit (33.8688 MHz).
75 AVSS3
Power supply for X'tal. (GND)
AVSS2
Power
77 N R PW M
0 Outputs PWM for R-ch. (Negative Phase)
78 RPWM
0 Outputs PWM for R-ch. (Positive Phase)
79 D S T 2
T e s t oin for DAC. Normal used state : fL1
I
slot. LR clock (f = FS).
slot)
slot)
interface. Bit clock.
slot)
signal output.
sional
data. [H] at
for X'tal.
for PWM driver.(GND)
MBS first)
,
I
1