Motorola A920 Service Manual page 94

A920: GPS
GPS ANTENNA
PIFA
M6050
FL6055
U6051
FL6050
Y6050
24.5535MHz
Description
The 1575.42 MHz satellite signal can be received through the GPS antenna PIFA_Planar Inverted F Antenna) or exernal GPS antenna. GPS signal received through the
PIFA will pass through FL6055 and LNA U6051. The signal is then passed to the LNA input of U6050 through FL6050.
The input signal at the LNA of U6050 is a Direct Sequence Spread Spectrum (DSSS) signal at 1575.42MHz with a 1.023 Mbps Bi-Phase Shift Keying (BPSK) modulat-
ed spreading code. The DSSS signal is then injected into an image reject mixer. The Mixer and on-chip 1565.97 MHz VCO will produce an IF center frequency of
9.45MHz. An IF filter is required between the Mixer and AGC Amplifier to provide an anti-aliasing function before A/D conversion. The IF filter block also contains an
I-Q phase shift combiner. This circuit properly phase shifts and sums the I and Q outputs from the image reject mixer to a single channel. The AGC amplifier provides
the additional gain needed to optimally load the signal range of the 2-bit A/D Converter. The 2-bit A/D onverter will then provide signal and magnitude output bits to the
Interface Block. The outputs of the Interface Block provide clocks and the 2-bit sample data to the CGSP2e/LP(U6000). These signals use single-ended PECL(Positive
Emitter-Coupled Logic) signaling to simplify the complexity of this interface. The interface block inputs are the single-wire AGC interface, (AGCDAT) and the Power
Control pin (PWRCTL).
The GPS DSP within U6000 correlates the incoming MAG and SIGN data. Wide parallel search architecture enables simultaneous search of 1,920 time/frequency bins
which enables a powerful combination of very fast reacquisition along with the capability to find and track very weak signals. The UART residing in U6000 is used to
interface data information between the GSP2e/LP(U6000) and POG. An integrated GPIO unit provides support for a variety of peripherals.
RTC is an ultra-low power implementation of a high precision 32-kHz driven clock derived from the PCAP. It is separately powered by the VDDRTC to allow maximum
battery life by maintaining time for the next power on. REF_FREQ is used as an external clock source for U6000.
GPS_WAKEUP* is an active low signal from POG to wake up SiRFLoc client from the deep sleep mode. GPS_RESET* is an active low hard reset signal for the SiRF
BB IC and Flash. GPS_BOOT_SEL is used by POG to set boot configuration upon reset. GPS_TIME_SYNC is an active high signal to provide time stamping of the pre-
cise time aiding that is sent over from POG over the UART.
EXT GPS
ANTENNA
I
IF Filter
&
Q AGC
IQ Combiner
÷41
38.194MHz
÷7
ø
49.107MHz
÷9
U6050
X2
Control
SiRF
RF to IF
SW_VGPS_RF_2_775V
VGPS_EXTANT_2_775V
REF_FREQ
Harmony
Lite
CLK_32_768K
PCAP
U6002
RTC
MAG
A/D
SIGN
AGCDAT
GPS/WAAS
DSP
ACQCLK
GPSCLK
GPS_GPIO3
Bias
GPIO
PWRCTL
UNIT
U6003
Q6050
U6001
GPS FLASH
1MB
GPS_BOOT_SEL(ED0)
GPS_RESET*
BUS INTERFACE
U6000
SiRF
Baseband
GPS_WAKEUP*
GPS_RX
DUAL
UART GPS_TX
GPS_TIME_SYNC
VGPS_RF_2_775V
VRF_RX_2_775V