The clock source for the Harmony Lite (HLite) is a 15.36Mhz oscillator (TCXO). Y130 is used to generated the 15.36MHz clock source. AFC for Y130 is controlled by
the Harmony Lite sequence manager via the AFCDAC line. The 15.36MHz clock source is enabled by an internal SPI bit and external control signal coming from
15.36M_CLK_EN*). The 15.36MHz clock source provides clocks to all A/Ds, DACs, external references and internal digital circuits of the Harmony Lite. In addition,
clock references are generated for the POG, RX and TX RF circuits.
The WCDMA VCO(U140) has a frequency range of 2.3G thru 2.36GHz, supplying both the receiver and transmitter with an LO. The control range is controlled by
HARMONY_LITE with a control range between 0.5 - 2.5V, with an output power @ ~-3 - 3dBm. The WCDMA VCO output frequency is controlled by an internal
phase lock loop (PLL) synthesizer. The phase locked loops use a fractional loop divider to permit fast lock times and low phase noise on their output signals. The VCO
output frequency is fed into a prescalar and devided down into a desired comparison frequency. The 15.36MHz reference frequency is also divided down into a compari-
son frequency. The two divided frequencies are then compared with a phase detector. The phase detector will then drive the charge pump. The charge pump output is pro-
cessed by the external loop filter and drives the tunable resonant network, altering the VCO frequency and closing the loop.
The superfilter block is used to provide a filtered supply voltage to the WCDMA VCO.