Helen - Motorola A920 Service Manual

A920:

Helen

Battery
FLASH
256 Mbit
SDRAM
256 Mbit
Bluetooth
POG
PCAP
Description
The Helen(adjunct processor) is a dual core processor architecture which incorporates a high-performane TI925T MPU core and a TI TMS320C55x DSP core. The fol-
lowing provides a brief description of the cores and associated peripherals being used in this design.
·Flash I/F, SDRAM I/F - Interfaces to FLASH and SDRAM
·Keypad Interface
·LCD I/F - Display Interface
·UART3 - IrDA interface
·MMC interface
·GPIO - For A/Ds
·Secondary SPI - PCAP interface
·Bluetooth Interface
·Camera IF - Backend Pixel Processor interface
Helen
1 Wire
Bus
FLASH
I/F
DMA
SDRAM
I/F
RAM RTC
1.5Mb
Internal
HP0
XCVR
USB
HP2
(host)
Single
HP1
Ended
IPCL
Converter
McBSP2
(SAP)
Secondary SPI
USB
(client)
USB Client
UART1
CE Bus
·I2C - Inter-Integrated Circuit Master and Slave interface
·IPCL - Inter-Processor Communications Link for Helen to POG interface
·ULPD - Ultralow-Power Device
·1 wire Communication for Battery EPROM
·USB(client) - Helen USB is used as a client, signals are routed through PCAP's USB transceiver
·UART1 - RS232 interface to CE bus
·McBSP1 - Multichannel Buffered Serial Port (VSAP) for the PCAP stereo audio interface
·McBSP2 - Multichannel Buffered Serial Port (ASAP) for the PCAP and Bluetooth audio interface
GPIO uWIRE
ARM925
icache
API 16KB
dcache
Bridge 8KB
MMU icache
12KW
C55x
DSP
SRAM
48kW
DRAM
32kW
ULPD
LCD
Camera
I
32kHz 12MHz
I/F IF
OSC OSC
Backend
Pixel
Image
12 MHz
Display Processor
Sensor
MMC/SD
MMC
IrDA
UART3
MCSI2
MCSI1
UART2
Bluetooth
Audio
PCAP
McBSP3
Codec
PCAP
Stereo
McBSP1
Codec
Keypad
2
C
8x8
Keypad