4-5 CPU PORT ALLOCATION (continued)
Pin
Line
No.
Name
[FUNC] input.
114
FUNC
L= Pushed.
115 VR_STB Electric volume IC strobe.
IF demodulator IC chip enable.
116
IFCON
L=Activated.
CPU clock output. (For tuning voltage
117
CKOUT
generation)
118
BEEP
Beep sounds. (Square waves)
Noise level detection.
119
NOISE
L=Squelch close.
The voltage from the external power
120
HVDET
supply or attached battery pack.
L=Power source detection.
PLL IC serial data.
121
PDAUL
PLL IC strobe.
122
PSTB
PLL IC serial clock.
123
PCK
[ ] input.
124 POWER
L=Pushed.
PLL IC power save mode control.
125
PPS
L=While in the power save mode.
Doubler circuit (DBL1; Q31, D44,
D47) control.
126
DBL2
L= While receiving 494.2–833 MHz
and 1066.7–1309.995 MHz.
Main power swtich (LOGIC UNIT:
127
PCON
Q103) control.
L=IC-R6 is power ON.
+3S line control.
128
+3SC
L=Receiving.
Description
I/O
I
O
O
O
O
I
I
O
O
O
I
O
O
O
O
4 - 5
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