Sony SSC-DC50A Service Manual page 43

CXD2480R-T4 (SONY)
C-MOS TIMING CONTROLLER WITH CCD DRIVERS
—TOP VIEW—
37 24
38 23
39 GND GND 22
40 21
41 V 20
DD
42 V 19
L
43 18
44 V 17
H
45 16
46 15
47 GND 14
48 13
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 I DCIN 25 O WEN
2 — NC 26 O MCK
3 — AV 3 27 I TEST2
DD
4 O H2 28 — V
DD
5 O H1 29 I RST
6 — GND 30 — GND
7 O RG 31 I OSCI
8 — AV 2 32 O OSCO
DD
9 — AV 1 33 — GND
DD
10 O XSHD 34 I CKI
11 O XSHP 35 — V
DD
12 O XRS 36 I TEST1
13 O ADCK 37 O V1
14 — GND 38 O V2
15 O LLPDM 39 — GND
16 O PBLK 40 O V3
17 I SEN 41 O V4
18 I SDAT 42 — VL
19 I SCK 43 O SUB
20 — V 44 — VH
DD
21 O ID 45 O CPP3
22 — GND 46 O CPP2
23 I HD 47 O CPP1
24 I VD 48 O DCOUT
34
CKI
32
OSCO
31
OSCI
TIMING GENERATOR
1/2
26
MCK
16
PBLK
15
CLPDM
21
ID
25
WEN
19
SCK
MODE SET
17
SEN
LATCH
18
SDAT
1
DCIN AMP
29
RST RESET
36
TEST1
27
TEST2
SSC-DC50A/54A (UC)
SSC-DC50AP/54AP/58AP (CE)
INPUT
31 32
CKI
OSCI OSCO
1 48
DCIN
DCIN DCOUT
34 26
HD
CKI MCK
23 16
OSCI
HD PBLK
24 15
RST
VD CLPDM
21
19
ID SCK
SCK
18 25
SDAT
SDAT WEN
17 11
SEN
SEN XSHP
10
TEST1, TEST2
XSHD
12
VD
XRS
13
ADCK
7
OUTPUT
RG
5
ADCK
H1
4
CLPDM
H2
37
CPP1 - CPP3
V1
38
DCOUT
V2
40
V3
41
H1, H2
V4
43
ID
SUB
47
MCK
CPP1
36 46
OSCO
TEST1 CPP2
37 45
PBLK
TEST2 CPP3
RG
RST
SUB
29
V1 - V4
WEN
XRS
XSHD
XSHP
11
XSHP
XSHP
10
XSHD XSHD
DRIVER
12
XRS XRS
13
ADCK
ADCK
7
RG DRIVER RG
5
H1
H DRIVER
4
H2
44
VH
42
VL
37
V1
38
V2
V DRIVER 40
V3
41
V4
43
SUB DRIVER
SUB
47
CPP1
CHARGE
46
CPP2
PUMP
45
CPP3
48
DCOUT
; CLOCK
; OPERATIONAL AMPLIFIER INPUT FOR GENERATING
THE SUB CLAMP VOLTAGE
; HORIZONTAL SYNC SIGNAL
; OSCILLATOR
; RESET
; SERIAL COMMUNICATION CLOCK
; SERIAL COMMUNICATION DATA
; SERIAL COMMUNICATION STROBE
; TEST
; VERTICAL SYNC SIGNAL
; A/D CONVERTER CLOCK
; CLAMP PLUSE FOR CCD DUMMY SIGNAL
; CHARGE PUMP CAPACITORS
; OPERATIONAL AMPLIFIER OUTPUT FOR GENERATING
THE SUB CLAMP VOLTAGE
; CCD HORIZONTAL REGISTER DRIVE PULSES
; LINE IDENTIFICATION SIGNAL
; MODULATION CLOCK (1/2 CKI)
; OSCILLATOR
; BLANKING CLEANING PULSE
; CCD RESET GATE DRIVE PULSE
; CCD ELECTRON-CHARGE DRAIN PULSE
; CCD VERTICAL REGISTER DRIVE PULSES
; WRITE ENABLE SIGNAL
(ONLY IN LOW-SPEED SHUTTER OPERATION)
; A/D CONVERTER SAMPLE AND HOLD PULSE
; SAMPLE AND HOLD PULSE FOR DATA
; SAMPLE AND HOLD PULSE FOR PRECHARGING
MB88346BPFV (FUJITSU)FLAT PACKAGE(SMALL)
MB88346BPFV-EF
C-MOS 8-BIT D/A CONVERTER
—TOP VIEW—
1 20
GND
GND
AO3 2 19 AO2
OUT OUT
AO4 3 18 AO1
OUT OUT
AO5 4 17 DI
OUT IN
AO6 5 16 CK
OUT IN
AO7 6 15 LD
OUT IN
AO8 7 14 DO
OUT OUT
AO9 8 13 AO12
OUT OUT
AO10 9 12 AO11
OUT OUT
10 V V 11
DD CC
AO1 - AO12 : 8-BIT D/A OUTPUTS
CK : CLOCK INPUT
DI : SERIAL DATA INPUT
DO : DATA OUTPUT
LD : DATA LOAD CONTROL INPUT (H : LOAD)
8
D0
D1
D2
17
DI
D3
D4
D5
D6
16
D7
CK
D8
D9
12
ADDRESS
D10 DECODER
D11
15
LD
18
AO1
19
AO2
2
AO3
3
AO4
4
AO5
17 5
D1 AO6
6
AO7
7
AO8
8
AO9
9
AO10
12
AO11
13
AO12
16
14
DO
LD
15
8-BIT
8 8-BIT 8
R-2R + 13
LATCH AO12
_
D/A CONV
8-BIT
8 8-BIT 8
R-2R + 18
LATCH AO1
_
D/A CONV
14
DO
IC
6-5