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6. Interrupt Controller Usage
PCI-FRM01 has interrupt controller to handle the hardware interrupt for each I/O device.
When you use these interrupts, eliminating the use of polling overhead of the process can be reduced.
I/O Address
Function
Offset
INTERRUPT
To control 82C55 ports, first the mode have to set up through the control register. To all setup, most
significant bit(MSB) is set to high "1" and write to the control register. If the MSB is "0", it will be
command of PORTC. (For more information, refer 82C55 manual)
When the first time power is applied, all ports will be the input and operation modes will be 0.
(1) INT_STA (Interrupt Status)
Indicates the current interrupt device that requires. To appear in the status register will have to make
the handle. When the write operation, status bits are cleared.
31
Bit
Name
0
1
2
3
4
5
6
UART
7
8
9
10
Register
B0h
INT_STA
B4h
INT_SEL
B8h
INT_EN
BCh
INT_SRC
INTERRUPT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Differential RS232C interface
Reserved
Reserved
Reserved
Reserved
2005 DAQ system, all rights reserved.
PCI-FRM01 Register Level Application Guide
Interrupt Status Register (Read Only)
Interrupt Status Clear (Write Only)
Interrupt Enable Register (Read/Write)
Interrupt Source Indicatior(Read Only)
Status Register Bit Position & meaning
16
15
14
13
12
11
G
S14
Description
Application Note
Description
10
9
8
7
6
5
4
Status
Default Value
http://www.daqsystem.com
(AN241)
3
2
1
0
S0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
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