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11
Interrupt
12
LVDS
13
14
15
Global
31-16
Reserved
For more information, refer AD5324 manual.
(2) INT_SEL
Select the Level Trigger and Edge Trigger of Interrup Input.
31
If it is "0", it is a Level Trigger. If it is "1", it is a Rising Edge Trigger.
(3) INT_EN
Each interrupt source is to enable the interrupt.
31
If each bit is '1', the device interrupt for corresponding bit will be enabled.
The bit 15 is Global Interrupt Enable. This bit is set to '1' to enable all interrupts.
(4) INT_SRC
INT_STA appear on the register, the interrupt request output of the device is latched at the rising
edge of the signal. Thus, it is not Level Trigger, it is an indication of Edge Triggere.
So, it can be cleared and requested the interrupt. On the other hand, in the INT_SRN, it represents
current output signal state of the current device.
31
Reserved
Reserved
Reserved
Reserved
When any of the above interrupt sources need
the processing, it will be changed '1'.
For future use
INTERRUPT
Reserved
INTERRUPT
Reserved
INTERRUPT
Source Indicator Bit Position & meaning
Reserved
2005 DAQ system, all rights reserved.
PCI-FRM01 Register Level Application Guide
Clear Register Bit Position & meaning
16 15
14
13
12
11
R
C14
Enable Register Bit Position & meaning
16
15
14
13
12
11
G
E14
15
14
13
12
11
S14
Application Note
10
9
8
7
6
5
4
Status Clear
10
9
8
7
6
5
4
Enable
10
9
8
7
6
5
4
Interrupt Source
http://www.daqsystem.com
(AN241)
'0'
'0'
'0'
'0'
'0'
All '0'
3
2
1
0
C0
3
2
1
0
E0
3
2
1
0
S0
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