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Circuit Description
Potentiometer VR3601 located on the VR
Unit. A Sample of the pre-amplified audio @
600 &2 is also delivered to the REC jack on the
rear Panel.
In the AM, SSB and CW modes, when the
noise blanker is on, a Portion of the 455 kHz
2nd IF Signal is tapped from the output of
plifiers 41004 & QlOO5 (3SK131-V12), and de-
tected by D1003 & D1004, then fed back to the
amplifiers Q1004 &' QlOO5, controlling their
signed so that noise pulses detected at D1003
blanking Signal is returned to the noise blank-
ing gate Controller (D1009, DlOlO & D1014),
switching them off during the noise pulse and
preventing the 2nd IF Signal from reaching
the narrow IF filters while the noise is present.
with a selectable fast or slow decay. The out-
put Signal from buffer amplifier QlOl9 is rec-
tified by AGC detector D1026 and D1027
plifier Q1020 (2SC2712). The Signal is proc-
essed by QlOl5 (2SJ125), then amplified again
by Q1014-1 and delivered to QlOll, QlOl8,
and Q1017 to control amplifier gain, S-meter
and squelch level.
PLL Frequency Synthesizer
The PLL section on the Local Unit consists
of Main Loop, DDS and the 2nd local oscilla-
tor circuitry. The PLL IC Q2030 (CX-7925B)
contains a reference oscillator/divider, serial-
parallel data latch, programmable divider,
and a Phase comparator.
1st
The 1st local Signal (47.260 - 77.210 MHz)
is generated by PLL Synthesis under control of
CPU on the Local Unit. In the main loop, one
of VCOs Q2015-Q2018 is activated by the
CPU and selected via Q2040 (M54564P) ac-
output of the selected VCO is buffered by
Q2045 (2SK192) and Q2011 (2SC535) before
delivery to mixer Q2012 (uIIX1037H)This sig-
low-pass filtered, buffered by Q2021(2SK192)
and amplified by Q2024 (2SC535) before be-
ing returned to PLL IC Q2030.
In the main divider/phase comparator sec-
tion of PLI, IC, the VCO Signal is divided by
128, according to a control Signal (serial di-
vider programming data) from the CPU to
produce 83. .92 kHz.
This Signal is then applied to the Phase
detector section for Phase-comparison with
the 10.4875 MHz reference Signal from the
OSC UN IT. Any Phase differente between the
two Signal will produce a 5-V pulsed-DC out-
put with pulse duration depending on the
to DC by charge pump 42025 (2SK184) and
Q2023 (2%3732),and low-pass filtered to pro-
then is applied to the varactor D2002 - D2005
VCO oscillating frequency to be Phase-locked
to the 10.4875 MHz reference.
The PLL, local Signal for Loop 1 is the prod-
uct of either Loop 1 Local Mixer (Q2012), or
the product of the output of this mixer further
mixed with the 10.4875 crystal reference sig-
nal, according to the band of Operation.
2nd Local Signal Generation
A Portion of 2nd local oscillator Signal
( 4 6 . 7 5 5 M H z ) , which is derived from
ation and passing through the LPF formed by
The sampled reference Signal (10.48576
MHz), which is generated by Q2030, is halved
by frequency divider 42032-2. The output
from the divider (5.24288 MHz) is low-pass
filtered, then mixed with the DDS output
(286.16 - 368.07 kHz) in mixer Q2034
(SN1 6913), which is also controlIed by the
MPU. The output from Q2034 is band-pass
filtered (5.57 MHz) by CF2001 before delivery
to mixer Q2028 (SN16913) along with the 2nd
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