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Circuit Description - Yaesu FRG-100 Technical Supplement

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This description, together with the block
diagram, is intended to provide a general un-
derstanding of the electrical functions of the
circuits of the FRG-100. Such an under-
standing is necessary for troubleshooting the
details.
Front-End Stages
Incoming RF from the antenna jack is deliv-
ered to the main unit after passing through a
tenna is selected using the rear-Panel switch)
and surge suppresser D1005, which removes
high voltage electrostatic pulses which might
otherwise darnage components in the front-
end. It is then low-pass filtered and attenu-
ated (if enabled). The received Signal is then
impedance transformed by transformer
T1018, then band-pass filtered to suppress in-
termodulation by Signals from other bands.
The correct bandpass filter is selected by BCD
control Signals from the PLL unit, and de-
then once again impedance transformed by
T1005, before entering the 1st mixer Stage.
The Signal then enters the balanced 1st
mixer,
consisting
output from the local unit (47.260 w 77.210
MHz) which has been amplified by Q1006
ing 47.21 MHz 1st mixer product Passes
through monolithic crystal filters XFlOOl and
XF1002 ( f 20 kHz BW) where other unwanted
mixer products are stripped away to produce
the filtered 1st IF Signal.
The filtered 1st IF Signal is then amplified
by Q1011(3SK179), and applied to balanced
2nd mixer QlOlO & Q1012 (2SK302x2), which
also receives the 2nd local Signal generated
from 46.775 MHz crystal X2002 and amplified
by QlOO8 (2SC2620), to produce the 455 kHz
o f Q1009/Q1013

Circuit Description

2nd IE When FM Operation is selected, a por-
tion of this 455 kHz product of the 2nd mixer
is buff er-amplified by QlO38 and delivered to
the optional FM
installed) For other modes, the 455 kHz Signal
is Passes through the noise blanker gate
by ceramic filters CF1 001, CF1002, or CF1 003
(depending on selected mode) where other
Final IF amplification is provided by
Ql018, QlO17, and Q1016 (3SK131-V12) be-
fore the Signal is applied to buffer amplifier
tion circuitry.
For SSB and CW modes, the amplified IF
sisting of D1033, D1038, DlO39, and D1040
priate BFO(carrier) Signal for either LSB, CW
or USB from the DDS unit, having been buff-
ered by Q1028. The detected Signal then
Cl141 before delivery to analog switch Q1023-
4. The Signal enters the active filter Ql026-1,
which functions as a low pass filter for audio
before delivery to analog switch Ql501.
For AM reception, another buffered output
from the 2nd IF is detected by D1032, the
output of which serves as both the detected
AM Signal and AGC. This Signal then Passes
through the LPF formed by R1208 and Cl130
before delivery to analog switch Q1023-3 and
on for audio amplification.
Aud io Amp lif iers
The low level detected audio in all modes
pass through mute switch Q1023-l(when not
muted by the squelch control lines), and then
buffer amplifier Q1026-2. The Signal Passes
through another mute circuit Q1031 & (21046
from the microprocessor having passed
through the LPF and VR1005. The mixed
audio is amplified by Q1034 (TDA2003H) to
drive a 4 w 8 Q loudspeaker or headphone.
The output from Q1034 is controlled by VOL
00 for detection(when

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