Akai LCT2715 Service Manual page 42

LP2996
DDR Termination Regulator
General Description
The LP2996 linear regulator is designed to meet the JEDEC
SSTL-2 specifications for termination of DDR-SDRAM. The
device contains a high-speed operational amplifier to provide
excellent response to load transients. The output stage pre-
vents shoot through while delivering 1.5A continuous current
and transient peaks up to 3A in the application as required
for DDR-SDRAM termination. The LP2996 also incorporates
a V pin to provide superior load regulation and a V
SENSE
output as a reference for the chipset and DIMMs.
An additional feature found on the LP2996 is an active low
shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low the V
tri-state providing a high impedance output, but, V
remain active. A power savings advantage can be obtained
in this mode through lower quiescent current.
Typical Application Circuit
© 2003 National Semiconductor Corporation
Features
n Source and sink current
n Low output voltage offset
n No external resistors required
n Linear topology
n Suspend to Ram (STR) functionality
n Low external component count
n Thermal Shutdown
REF
n Available in SO-8, PSOP-8 or LLP-16 packages
Applications
output will n DDR-I and DDR-II Termination Voltage
TT
will
n SSTL-2 and SSTL-3 Termination
REF
n HSTL Termination
DS200575
November 2003
20057518
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