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5-23. IC PIN FUNCTION DESCRIPTION
• SERVO BOARD IC301 CXD2652AR
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Pin No.
Pin Name
1
MNT0
2
MNT1
3
MNT2
4
MNT3
5
SWDT
6
SCLK
7
XLAT
8
SRDT
9
SENS
10
XRST
11
SQSY
12
DQSY
13
RECP
14
XINT
15
TX
16
OSCI
17
OSCO
18
XTSL
19
RVDD
20
RVSS
21
DIN
22
DOUT
23
ADDT
24
DADT
25
LRCK
26
XBCK
27
FS256
28
DVDD
29 to 32
A03 to A00
33
A10
34 to 38
A04 to A08
39
A11
40
DVSS
41
XOE
42
XCAS
43
A09
44
XRAS
45
XWE
I/O
Focus OK signal output to the MD mechanism controller (IC501)
O
"H" is output when focus is on ("L": NG)
O
Track jump detection signal output to the MD mechanism controller (IC501)
O
Busy monitor signal output to the MD mechanism controller (IC501)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
I
Writing serial data signal input from the MD mechanism controller (IC501)
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
I
Reset signal input from the MD mechanism controller (IC501) "L": reset
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
O
"L" is output every 13.3 msec
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
O
"L" is output every 13.3 msec
Laser power selection signal input terminal
I
"L": playback mode, "H": recording mode (fixed at "L" in this set)
O
Interrupt status output to the MD mechanism controller (IC501)
Recording data output enable signal input terminal
I
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at "L")
I
System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
Input terminal for the system clock frequency setting
I
"L": 45.1584 MHz, "H": 22.5792 MHz (fixed at "H" in this set)
—
Power supply terminal (+3.3V) (digital system)
—
Ground terminal (digital system)
I
Digital audio signal input terminal when recording mode Not used (fixed at "L")
O
Digital audio signal output terminal when playback mode Not used (open)
I
Recording data input terminal Not used (fixed at "L")
O
Playback data output to the CXD2726Q (IC805)
O
L/R sampling clock signal (44.1 kHz) output to the CXD2726Q (IC805)
O
Bit clock signal (2.8224 MHz) output to the CXD2726Q (IC805)
O
Clock signal (11.2896 MHz) output terminal Not used (open)
—
Power supply terminal (+3.3V) (digital system)
O
Address signal output to the D-RAM (IC307)
Address signal output to the external D-RAM Not used (open)
O
O
Address signal output to the D-RAM (IC307)
O
Address signal output to the external D-RAM Not used (open)
—
Ground terminal (digital system)
O
Output enable signal output to the D-RAM (IC307) "L" active
O
Column address strobe signal output to the D-RAM (IC307) "L" active
O
Address signal output to the D-RAM (IC307)
O
Row address strobe signal output to the D-RAM (IC307) "L" active
O
Write enable signal output to the D-RAM (IC307) "L" active
Description
Almost all, "H" is output
Almost all, "H" is output Not used (open)
47
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