Zte ZXR10 5900 Product Description page 61

four priority classes, and messages of different priorities are accepted and rejected
based on the depth of the message queues dynamically monitored), and different
algorithms (for example, strict priority, weighted round robin, etc.) are used for the
implementation.
The process communication sub-module can also implement process communication,
both intra-processor and inter-processor, through asynchronized messages. Two
suspension mechanisms are provided for the sending of messages: Timeout suspension
and no suspension.
Timer and Clock Management

Every process can be set with multiple timers for triggering timing service and timeout
processing. There are relative timers and absolute timers. Relative timers include single-
time and cyclic timers according to the times of activation. Depending on whether the
period of the timer is configurable, there are named timers and nameless timers. A
named timer is a timer whose period can be modified on-line by using OAM
configuration. In addition, ROS also supports timers with random ∆ delay.
Timers are handled in a way that they are appended to the queue when they expire. The
timing period actually used is divided into segments, and the timer control module
describes the appropriate queue indexes. Therefore, the inserted delay is basically
constant, and it is not necessary to find the insertion position in the timer queue every
time when a new timer is set, since it can be simply appended to the tail of the queue.
However, or timers longer than 999.9S and absolute timers are still managed in the old
way that is based on a single queue.
 Memory Management
The buffer is an important resource of the system. To efficiently use limited memory
resource and minimize memory fragments, requests from the application layers for the
buffer are handled differently in the design of the module. When the needed buffer is
greater than 8192 minus the memory block of the description header information of the
buffer, one buffer will be obtained from buffer areas of 64, 128, 256, 512, 1024, 2048,
4096, and 8192 specified by the ROS. Other needs for large memory obtain the buffer
areas by using the heap management module of the ROS. The buffer areas of each size
are managed in a queue, with the function interface for request and return provided. The
buffer queue is a simple cyclic queue. At request, one idle block is taken from the head
of the queue, and at return, the block is returned to the tail of the same queue. Since
every task of the system will request and return the buffer queue, mutual exclusion
control must be enforced. Every buffer has a memory control block (MCB), which
records the queue of that buffer and its occupation flag. At the request for a pointer and
return of a pointer, the MCB prevents invalid memory from being returned to the queue.
The MCB will check the simple memory access out-of-bound errors and perform
appropriate processing by invoking the specified hook program. In the debug version,
the boards with hardware MMU can monitor memory overrun by MMU.
In the module, heap management only performs simple encapsulation of the memory
management allocation function of the VxWorks. The heap space is determined during
execution. The space from the high-end of the physical memory to the highest end
occupied by the system with the specified memory block space excluded is created as a
separate MEM area of the VxWorks for heap management. Similarly, memory allocation
and release of the heap are subjected to measurement and memory out-of-bound check.
System Control

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