Vizio L37 Service Manual
Vizio L37 Service Manual

Vizio L37 Service Manual

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Service Manual

Model #: VIZIO L37
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential

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Table of Contents
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Summary of Contents for Vizio L37

  • Page 1: Service Manual

    Service Manual Model #: VIZIO L37 V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099 Top Confidential...
  • Page 2: Table Of Contents

    8. Waveforms 9. Trouble Shooting 10. Block Diagram 10-1 11. Spare parts list 11-1 12. Complete Parts List 12-1 Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram VIZIO L37 Service Manual...
  • Page 3 Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards. VIZIO L37 Service Manual...
  • Page 4: Features

    Chapter 1 Features 1. Built in TV channel selector for TV viewing 2. Simulatnueous display of PC and TV images 3. Connectable to PC’s analog RGB port 4. Built in s-video, HDTV, composite video, HDMI ,TV and DTV out 5. Built in auto adjust function for automatic adjument of screen display 6.
  • Page 5: Specifications

    Chapter 2 Specification 1. LCD CHARACTERISTICS Type: WXGA TFT LCD Size: 37 inch Display Size: 37.02 inches (940.3mm) diagonal Outline Dimension: 877.0/878.0 mm (H) x 516.8 mm (V) x 55.5 (D) mm (Typ.) Pixel Pitch: 0.200mm x 0.600mm x RGB Pixel Format: 1366 horiz.
  • Page 6 b. Signal Level Video (Y): Analog 0.1Vp-p/75 Video (C): Analog 0.286p-p/75 Sync (H+V): 0.3V below Video (Y) c. Frequency H: 15.734KHz V: 60Hz (NTSC) 3.2.3 F-Type TV RF connector 3.2.3.1 NTSC System: a. Signal Level: Analog 1Vp-p typical(45dB~90dB) b. System :NTSC c.
  • Page 7 b. Signal Level Video (R, G, B) : Analog 0.7Vp-p/75 Sync (H, V) : TTL level c. Sync Type TTL (Separate / Composite) or Sync. On-Green d. Sync polarity Positive or Negative e. Frequency : H: support to 30K~70KHz V: support to 50~85Hz Pixel Clock: support to 110MHz 3.2.5 HDMI Signal (Digital HD): a.
  • Page 8 b. Type: TYPE A c. Polarity: Positive or Negative d. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) CONFIDENTIAL – DO NOT COPY Page 2-4 File No. SG-0176...
  • Page 9 3.2.6 Component signal (Analog HD1 and Analog HD2) 3.2.6.1 Analog HD1 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c.
  • Page 10 8. DIMENSIONS (Physical dimension) Width: 959.9 Depth: 311.0 Height: 748.4 9. WEIGHT (Physical weight) a. Net: 25.9 b. Gross: 33.5 9-1. MOUNTING PRECAUTIONS (1) You must mount a module using holes arranged in four corners or four sides. (2) You should consider the mounting structure so that uneven force (ex. Twisted stress) is not applied to the module.
  • Page 11 9-2. OPERATING PRECAUTIONS (1) The spike noise causes the mis-operation of circuits. It should be lower than following voltage : V=±200mV(Over and under shoot voltage) (2) Response time depends on the temperature.(In lower temperature, it becomes longer.) (3) Brightness depends on the temperature. (In lower temperature, it becomes lower.) And in lower temperature, response time(required time that brightness is stable after turned on) becomes longer.
  • Page 12: On Screen Display

    Chapter 3 On Screen Display Main unit button Power Input CH ▲ CH ▼ VOL + VOL - MUTE / EXIT MENU TV Source A. PICTURE ADJUST: a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3) b. Adjust the BACKLIGHT (0~100) c.
  • Page 13 e. SKIP CHANNEL (YES/NO) D. PARENTAL CONTROL: a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT E. PIP SETUP: a. STYLE (OFF/PIP/POP) b. Source (AV1、AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD RGB、DTV) c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%)) d.
  • Page 14 C. AUDIO ADJUST: a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) D. PIP SETUP: a. STYLE (OFF/PIP/POP) b. SOURCE (AV1、AV2、AV3、TV) c.
  • Page 15 f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) i. AUDIO SOURCE(DIGITAL HD/DTV) C. PARENTAL CONTROL: a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c. MOVIE RATING d. ACCESS CODE EDIT D. PIP SETUP: a. STYLE (OFF/PIP/POP) b.
  • Page 16 B. AUDIO ADJUST: a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) C. PARENTAL CONTROL: a. PARENT LOCK ENABLE (ON/OFF) b.
  • Page 17 g. Adjust the SHARPNESS (0~100) B. AUDIO ADJUST: a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. BALANCE (0~100) e. SURROUND (ON/OFF) f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA) g. MUTE (ON/OFF) h. SPEAKERS (ON/OFF) C.DTV OSD a. DTV TUNER SETUP 1.
  • Page 18 2. DIGITAL COLOSED CAPTION α.OFF β.SERVICE1 γ.SERVICE2 δ.SERVICE3 ε.SERVICE4. ζ.SERVICE5 η.SERVICE6 3. DIGITAL CAPTION STYLE PRESS<OK> (1) AS BROADCASTER (2)CUSTOM FONT SIZE α.LARGE β.SMALL γ.MEDIUM FONT COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA FONT OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT BLACKGROUND COLOR α.BLACK β.WHITE...
  • Page 19 η.YELLOW θ.MAGENTA BLACKGROUND OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT WINDOW COLOR α.BLACK β.WHITE γ.GREEN δ.BLUE ε.RED ζ.CYAN η.YELLOW θ.MAGENTA WINDOW OPACITY α.SOLID β.TRANSLUCENT γ.TRANSPARENT c.PARENTAL CONTROL PASSWORD PRESS<OK> 1.0000 2.CHANNEL BLOCK PRESS<OK> D. PARENTAL CONTROL: a. PARENT LOCK ENABLE (ON/OFF) b. TV RATING c.
  • Page 20 F. SPECIAL FEATURES: a. LANGUAGE (ENGLISH/FRANCE/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. WIDE FORMAT (NORMAL/WIDE) d. RESET ALL SETTING CONFIDENTIAL – DO NOT COPY Page 3-9 File No. SG-0176...
  • Page 21: Factory Preset Timings

    Chapter4 Factory preset timings This timing chart is already preset for the TFT LCD analog & digital display monitors. Refresh Horizontal Vertical Horizontal Vertical Pixel Resolution rate Frequency Frequency Polarity Polarity Rate 640x480 60Hz 31.5kHz 59.94Hz 25.175 640x480 75Hz 37.5kHz 75.00Hz 31.500 800X600...
  • Page 22: Pin Assignment

    Chapter5 Pin Assignment The TFT LCD analog display monitors use a 15 Pin Mini D-Sub connector as video input source. Description Green Blue Ground Ground R-Ground G-Ground B-Ground +5V for DDC Ground No Connection (SDA) H-Sync (Composite Sync) V-Sync (SCL) Table 1.
  • Page 23 PC connector 15 pin male D-sub connector a. Pin Assignment Refer to Table 1 b. Signal Level Video (R, G, B): Analog 0.7Vp-p/75 Ω Sync (H, V): TTL level RGB Signal: a. Sync Type TTL (Separate / Composite) or Sync. On Green b.
  • Page 24 HDMI Signal (Digital HD): a. Pin Assignment Refer to Table 2. b. Type A c. Polarity Positive or Negative d. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) Four-Pin mini DIN S-Video Connector a.
  • Page 25 b. Signal Level Video (Y): Analog 0.1Vp-p/75Ω Video (C): Analog 0.286p-p/75 Sync (H+V): 0.3V below Video (Y) Frequency H: 15.734KHz V: 60Hz (NTSC) CONFIDENTIAL – DO NOT COPY Page 5-4 File No. SG-0176...
  • Page 26 F-Type TV RF connector NTSC System: a. Signal Level: Analog 1Vp-p typical(45dB~90dB) b. System :NTSC c. Frequency: 55~801MHz (NTSC) ATSC System a. IF-output level: 1Vp-p minimum b. System: ATSC c. Frequency: 57~863MHz(ATSC) Component signal (Analog HD1 and Analog HD2) Analog HD1 a.
  • Page 27 Analog HD2 a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p c. Impedance 75Ω RCA-type (Yellow) Composite Video Connector(AV1,AV2,AV3) a.
  • Page 28 PHONE JACK AUDIO INPUT a. Signal Level 1Vrms b. Frequency Response 250Hz-20KHz CONFIDENTIAL – DO NOT COPY Page 5-7 File No. SG-0176...
  • Page 29 Chapter 6 Block Diagram The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main board receives different types of video signal into the MTK8205 Ic. Afterward, the MTK8205 Ic process the signals control the various functions of the monitor and outputs control signal, video signal and power to the 37”...
  • Page 30 The function of the inverter is to step up the voltage supplied by the main board to the power that is needed to light up the lamps in the panel. Simultaneously, the digital video signals are processed in the panel and the outcome determines the brightness, pixel on/off and the color displayed on the panel.
  • Page 31 Main Board Block Diagram Video Signal RJ11 Audio Signal Communicate Signal 24C02 Control Pin HDMI FFC 50PIN CON. Sil9011 CON. For DTV Signal +12V +3.3V +2.5V 24C02 D_SUB 15PIN DC/DC FLASH DDR SDRAM BOARD MEMORY CONN. CONN. U11,U12 POWER CONN. COMPONENT1&2 IDTQS3VH257 VIDEO P8...
  • Page 32 Video Board Block Diagram Video Signal Audio Signal Communicate Signal Control Pin PORT SAW Narrow_IF_OP1&OP2 FILTER Amplifiers Demodulator MT5111 IF AGC PHILIPS TD1336 DDR SDRAM U12,U13 DTV Backend Decoder MT5351 50PIN CON. IDTQS3VH257 AUD_CTRL For Main Board DV33 VOLTAGE Flash Memory CONTROL CRYSTAL OSCILLATOR...
  • Page 33: Main Board I/O Connections

    Chapter7 Main Board I/o Connections J7 C → ONNECTION BOTTOM Description “Auto” “Left” “Right” “Down” “Gnd” “Up” “Menu” “Source” “Power” “LED” “IR” “+5V” J1 C →B ONNECTION OTTOM Description “POWRSW” “+12V” “+12V” “+12V” “GND” “GND” “GND” “GND” “+5V” “+5V” “+5V” “PWM”...
  • Page 34 J3 C →B ONNECTION OTTOM Description Description “+3.3V” “HPR” “GND” “HPL” “G/Y” “GNDV” “B/U” “HPDET#” “R/V” “AV3_IN” “LMAIN1” “AV3_GND” “RMAIN1” “AV3L” “+5.0 ” “AV3L GND” “GND” “AV3R” “8302IR” “AV3R GND” “8302NET1” “S1Y_IN” “8302NET2” “S1Y_GND” “8302RXD” “S1C_IN” “8302TXD” “S1C_GND” “GNDV” “SVDET2#” CONFIDENTIAL –...
  • Page 35 J2 C →B ONNECTION OTTOM Description Description “GND” “GND” “I2C_SW” “VOG3” “OREQUEST#” “VOG2” “OREADY#” “VOG1” “ORESET#” “VOG0” “GND” “GND” “VOPCLK” “VOB7” “VODE” “VOB6” “VOVSYNC” “VOB5” “VOHSYNC” “VOB4” “GND” “GND” “VOR7” “VOB3” “VOR6” “VOB2” “VOR5” “VOB1” “VOR4” “VOB0” “GND” “GND” “VOR3” “AO1SDATA0”...
  • Page 36 J8 C →B ONNECTION OTTOM Description “+5V” “GND” “GND” “+12V” “+12V” CONFIDENTIAL – DO NOT COPY Page 7-4 File No. SG-0176...
  • Page 37: Theory Of Circuit Operation

    Chapter 8 Theory of Circuit Operation The operation of D-SUB 15pin route The D-SUB 15pin is input analog signal to the MTK8205 transfer A/D converter then generates the vertical and horizontal timing signals for display device. The operation of HDMII CON route The HDMI CON is input digital signal the signal is process to the sil9011.
  • Page 38 1. The power key through POW and GND to control MTK8205, MTK8205 will receive a low signal to turn on or off system while press the power key. 2. The other key the same as power key . 3. The LED is constructed with two separate LED which color is blue and orange. The MTK8205 direct control the LED’s when MTK8205 (OGO5) is low the LED is orange (Close power) when MTK8205 (OGO5) is high the LED is blue (Open power).
  • Page 39 BOLOCK DIAGRAM 1. Video input a. Input Multiplexing 1.component X2 2.composite X3 3.s-videoX1 4.HDMI X1 5.VGA X1 6.RF X2 CONFIDENTIAL – DO NOT COPY Page 8-3 File No. SG-0176...
  • Page 40 b. Input formats: 1.support HDTV 480i/480p/720p/1080p 2.support Y/C signal 1VP-P/75Ω 3.support Y/C signal 1VP-P/75Ω 4.support 480i/408p/720p/1080i/1080p 5.support VGA input up to 1366x168@60HZ 6.support NTSC system Frequency 55~801MHZ 7. support ATSC system Frequency 57~863MHZ 2. TV Decoder For pip/pop: Dual identical TVD on chip 3D-comb for both path Dual VBI decoders for the application of V-chip 3.
  • Page 41 BOLOCK DIAGRAM 4. 2D-Graphic/OSD processor Two OSD planes. Support alpha blending among these two planes and video Support text/bitmap decoder Support line/rectangle/gradient fill Support bitblt Support color key function Support clip mask 65535/256/16/4/2-color bitmap format OSD Automatic vertical scrolling of OSD image Support OSD mirror and upside down CONFIDENTIAL –...
  • Page 42 5. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MTK8205 to initial state. After that the Reset will transits to high state and the MTK8205 start to work that microprocessor executes the programs and configures the internal registers.
  • Page 43 b. PIP/POP HARDWARE LIMITION: Secondary Window Source Primary Window Source C D E ATSC Tuner NTSC Tuner A/V1 A/V2 A/V3 (Side) Analog HD1 X X X X (480i~1080i) Analog HD2 X X X X (480i~1080i) Digital HD1 X X X X (HDMI) X X X X Input Matrix for Windowing Functionality...
  • Page 44 c. Scaling Arbitrary ratio vertical/horizontal scaling of video, from1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture in picture (PIP) Picture in picture d. Display 12/10 10/8 8/6 Dithering processing for LCD display 10bit gamma correction Support Alpha blending for Video and two OSD panel Frame rate conversion 7.
  • Page 45 8. Flash Usage Flash is used to store FW code, fonts, bitmaps, and big tables for VGA, Video, and Gamma 2Mbyte is recommended to build a general TV model MTK8205 Flash ROM support test report CONFIDENTIAL – DO NOT COPY Page 8-9 File No.
  • Page 46 DDR SDRAM (M13S128168A-6T) Application Pin description CONFIDENTIAL – DO NOT COPY Page 8-10 File No. SG-0176...
  • Page 47 Command Truth Table 1. Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT &...
  • Page 48 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.(To issue DLL reset command, provide “High” to A8 and “Low” to BA0) 7. Issue precharge commands for all banks of the device. 8.
  • Page 49 3. Precharge The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously.
  • Page 50 4. Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The DDR SDRAM has four independent banks; so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
  • Page 51 7. Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst.
  • Page 52 MX29LV160BTTC (Flash) Application The MX29LV800T/B & MX29LV800AT/AB is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV800T/B & MX29LV800AT/AB is packaged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP.
  • Page 53 BLOCK DIAGRAM 1. COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences.
  • Page 54 2. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory, the system must drive WE and CE to VIL, and OE to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four.
  • Page 55 After the system writes the auto select command sequence, the device enters the auto select mode. The system can then read auto select codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode.
  • Page 56 4. READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
  • Page 57 MT5111 Application: MT5111 Functional Block Diagram MT5111 is fully integrated single-chip 8-VSB , designed specifically for the digital terrestrial. HDTV receivers . The chip is fully compliant with the ATSC A/53 digital TV standard. MT5111 includes a 10-bit A/D converter , 8-VSB demodulator , TCM(Trellis-Coded Modulation).
  • Page 58 The carrier frequency offset and symbol timing offset are both estimated and compensated by a fully digital synchronizer . The synchronizer also controls the rate conversion in the digital re-sampling device by estimating the sampling frequency offset . All synchronization in MT5111 are integrated in digital circuits , no external VCXO is required.
  • Page 59 8 . 25MHZ crystal for clock generation 9 . Full-digital timing recovery , no VCXO is required 10. Full-digital frequency offset recovery with wide acquisition range –1MHZ~+1MHZ 11. Dual digital AGC control for IF and RF respectively 12. MPEG-2 transport stream output in parallel or serial format 13.
  • Page 60 General Feature List : A . Host CPU: 1. ARM 926EJ 2.16K I-Cache and 16K D-Cache 3. 8K Data TCM and 8K instruction 4. JTAG ICE interface 5. Watch Dog timers B . Transport Demuxer : 1. Support 3 independent transport stream inputs 2.
  • Page 61 G . Video Processing : 1. Advanced Motion adaptive de-interlace on SDTV resolution. 2. Support clip 3. 3:2/2:2 pull down source detection. 4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X. 5. Support Edge preserve. 6. Support horizontal edge enhancement. 7.
  • Page 62 M . Peripheral Bus Interface : 1. Support NOR/NAND flash. 2. Support CableCard host control bus. N . Audio : 1. Support Dolby Digital AC-3 decoding. 2. MPEG-1 layer I/II , MP3 decoding. 3. Dolby prologic II. 4. Main audio output : 5.1ch + 2ch ( down mix ) 5.
  • Page 63 MX29LV320BTTC (Flash) Application : The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.
  • Page 64 CONFIDENTIAL – DO NOT COPY Page 8-28 File No. SG-0176...
  • Page 65 BLOCK DIAGRAM CONFIDENTIAL – DO NOT COPY Page 8-29 File No. SG-0176...
  • Page 66 BUS OPERATION--1 Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 0.5V, V HH=11.5-12.5V, X=Don't Care,   AIN=Address IN, DIN=Data IN,DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment.
  • Page 67 BUS OPERATION--2 Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sectors , or the entire device.
  • Page 68 TABLE A. MX29LV320AT/B COMMAND DEFINITIONS Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA.
  • Page 69 STANDBY MODE MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±0.3V.
  • Page 70 The system can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/BY pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH.
  • Page 71 Table B. Write Operation Status Notes: 1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle. 2. Performing successive read operations from any address will cause Q6 to toggle. 3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"...
  • Page 72 Fig D. READ TIMING WAVEFORMS CONFIDENTIAL – DO NOT COPY Page 8-36 File No. SG-0176...
  • Page 73 Fig E. RESET TIMING WAVEFORM CONFIDENTIAL – DO NOT COPY Page 8-37 File No. SG-0176...
  • Page 74: Functional Description

    DDR SDRAM (NT5DS16M16CS-5T) Application : Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
  • Page 75 Block Diagram (16Mb x 16) Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
  • Page 76 Pin Configuration - 400mil TSOP II (x4 / x8 / x16) CONFIDENTIAL – DO NOT COPY Page 8-40 File No. SG-0176...
  • Page 77: Operating Mode

    Mode Register Operation Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values.
  • Page 78 Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition.
  • Page 79 Truth Table a: Commands 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are reserved;...
  • Page 80 Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;...
  • Page 81 Operations : Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access.
  • Page 82 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CONFIDENTIAL – DO NOT COPY Page 8-46 File No. SG-0176...
  • Page 83 Read Command Writes Write bursts are initiated with a Write command, as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst.
  • Page 84 Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
  • Page 85 Data Input (Write) Data Output (Read) WM8776 Application The WM8776 is a high performance, stereo audio codec with five channel input selector. The WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and other audiovisual equipment. Etch ADC channel has programmable gain control with automatic level control.
  • Page 86 BLOCK DIAGRAM 1. Audio sample rate The master clock forWM8776 supports DAC and ADC audio sampling rates 256fs to 768fs, where fs is the audio sample frequency (DACLRC or ADCLRC) typically 32KHZ, 44.1KHZ, 48KHZ or 96KHZ (the DAC also supports operation at 128fs and 192fs and 192KHZ sample rate).
  • Page 87 2. DIGITAL AUDIO INTERFACE a. Slave mode The audio interfaces operations in either slave mode selectable using the MS control bit. In slave mode DIN is always an input to the WM8776 and DOUT is always an output. The default is Slave mode. In slave mode (ms=0) ADCLRC, DACLRC, ADCBCLK, DACBCLK are input to the WM8776 .
  • Page 88: File No. Sg-

    2-wire serial interface as shown in the following figure. The wm8776 has two possible device addresses, which can be selected using the CE pin In the L37 LCD TV CE pin is LOW (device address is 34h). In the L37 wm8776 has 2-wire interface CONFIDENTIAL –...
  • Page 89 Sil9011 Application The sil9011 provides a complete solution for receiving HDMI compliant digital audio and video. Specialized audio and video processing is available within the sil9011 to easily and cost effectively adds HDMI capability to consumer electronics devices such as digital TVs, plasma displays, LCD TVs and projectors.
  • Page 90 1. TMDS Digital Core The core performs 10-to-8-bit TMDS decoding on the audio and video received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link clock rates to 165MHZ, including CE modes to 720P/1080I/1080P. 2.
  • Page 91 The receiver can also process the video data before it is output as show below figure 5. I c Interface to Display Controller The Controller I c interface (CSDA, CSCL) on the sil9011 is a slave interface capable of running up to 400KHZ. This bus is used to configure the SIL9011 by reading/writing to the appropriate registers.
  • Page 92 BLOCK DIAGRAM 1. I c Bus I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and received in the units of byte and Acknowledge. It is transmitted by MSB first from the Start conditions. The data format is set as shown in the following figure.
  • Page 93 2. Switch control table a. Video output 1 b. Audio output 1 c. Audio gain CONFIDENTIAL – DO NOT COPY Page 8-57 File No. SG-0176...
  • Page 94 TDA8946 Application In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an output power of 2 × 10 W at an 8 Ω load and a 12 V supply. Block diagram 1. Input configuration The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical.
  • Page 95 2. Output power measurement The output power as a function of the supply voltage is measured on the output pins at THD = 10%,in the L32 LCD TV Vcc=12V so we can see as shown in the following figure output about 7W. CONFIDENTIAL –...
  • Page 96 3. Mode selection In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the proper DC voltage to pin MODE. a. Mute — In this mode the amplifier is DC-biased but not operational (no audio output). This allows the input coupling capacitors to be charged to avoid pop-noise.
  • Page 97: Waveforms

    Chapter 9 Waveforms 1. PC MODE(1366X768 60HZ) CH1 H-sync (FB46); CH2 V-sync (FB45) GREEN (R194) CONFIDENTIAL – DO NOT COPY Page 9-1 File No. SG-0176...
  • Page 98 CH1 VGAHSYNC# (FB46); CH2 VGAVSYNC# (FB45) CH1 VGAVSYNC# (FB45); CH2 GREEN (R194) CONFIDENTIAL – DO NOT COPY Page 9-2 File No. SG-0176...
  • Page 99 CH1 VGAL (CE81); CH2 AVOL (R252) CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CONFIDENTIAL – DO NOT COPY Page 9-3 File No. SG-0176...
  • Page 100 CH1 XTALI (U9 PIN A15);CH2 XTALO (U9 PIN B15) AV&TV MODE (AV1/AV2/AV3/TV) VIDEO CH1 (R88); CH2 (Q4 PIN1) CONFIDENTIAL – DO NOT COPY Page 9-4 File No. SG-0176...
  • Page 101 CH1 CVBS1+ (U9 PINA2); CH2 CVBS1 (R136) CH1 AV1L (U20 PIN1); CH2 AUO1L_SWO (U20 PIN36) CONFIDENTIAL – DO NOT COPY Page 9-5 File No. SG-0176...
  • Page 102 CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CH1 D_CLK# (U11 PIN46);CH2 D_DQ15(U11 PIN65) CONFIDENTIAL – DO NOT COPY Page 9-6 File No. SG-0176...
  • Page 103 CH1 DACMCLK (U22 PIN11);CH2 DOUT (U22 PIN12) CH1 SCL34H(U22 PIN19);CH2 SDA34H (U22 PIN18) CONFIDENTIAL – DO NOT COPY Page 9-7 File No. SG-0176...
  • Page 104 ANALOG HD MODE (ANALOG HD1/HD2) CH1Y1_IN (R105); CH2 Y (U21 PIN7) CH1Y (R280); CH2 Y+ (C120) CONFIDENTIAL – DO NOT COPY Page 9-8 File No. SG-0176...
  • Page 105 CH1 TUL (U20 PIN44); CH2 AUO1L_SWO (U20 PIN 36) CH1 AUSPL (RA12) ; CH2 L+ (UA1 PIN17) CONFIDENTIAL – DO NOT COPY Page 9-9 File No. SG-0176...
  • Page 106 4. DIGITAL HD CH1 DATA2+ (P1 PIN 1); CH2 DATA2- (P1 PIN3) CH1 HDMI0 (U16 PIN 124) ;CH2 HDMI15 (U16 PIN 102) CONFIDENTIAL – DO NOT COPY Page 9-10 File No. SG-0176...
  • Page 107 CH1 XTLI (U16 PIN85) ;CH2 XTLO (U16 PIN86) CH1 HDMISDA (U16 PIN39);CH2 HDMISCL (U16 PIN40) CONFIDENTIAL – DO NOT COPY Page 9-11 File No. SG-0176...
  • Page 108 DTV Mode(Video Board): CH1 AO1BCK (J1 Pin 7) ; CH2 AO1SDATA0 (J1 PIN 9) CH1 VOPCLK (J1 Pin 44) ; CH2 VOB0 (J1 PIN 11) CONFIDENTIAL – DO NOT COPY Page 9-12 File No. SG-0176...
  • Page 109 CH1 VOPCLK (J1 Pin 44) ; CH2 VOG0 (J1 PIN 21) CH1 VOPCLK (J1 Pin 44) ; CH2 VOR0 (J1 PIN 31) CONFIDENTIAL – DO NOT COPY Page 9-13 File No. SG-0176...
  • Page 110 CH1 XTAL1 (C63) ; CH2 XTAL2 (C62) CH1 OPWM0 (R42) ; CH2 OXTALI (R43) CONFIDENTIAL – DO NOT COPY Page 9-14 File No. SG-0176...
  • Page 111 POWER ON/OFF CH1 DV120B (F1); CH2 GPIO (R3); POWER ON CONFIDENTIAL – DO NOT COPY Page 9-15 File No. SG-0176...
  • Page 112 CH1 DV120B (F1); CH2 GPIO (R3); POWER OFF CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER ON CONFIDENTIAL – DO NOT COPY Page 9-16 File No. SG-0176...
  • Page 113 CH1 DV50B (U7 PIN8); CH2 GPIO (R3); POWER OFF CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-17 File No. SG-0176...
  • Page 114 CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER OFF CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER ON CONFIDENTIAL – DO NOT COPY Page 9-18 File No. SG-0176...
  • Page 115 CH1 DV50A (U4 PIN1); CH2 DV33A (F3) AC POWER OFF CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER ON CONFIDENTIAL – DO NOT COPY Page 9-19 File No. SG-0176...
  • Page 116 CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER OFF CH1 DV50B(U14 PIN 3); CH2 DV25 (U14 PIN2) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-20 File No. SG-0176...
  • Page 117 CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) POWER OFF CH1 GPIO (R3); CH2 LVDS-SEQ (R10) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-21 File No. SG-0176...
  • Page 118 CH1 GPIO (R3); CH2 LVDS-SEQ (R10) POWER OFF CH1 GPIO (R3); CH2 ATSC-SW(R121) POWER ON CONFIDENTIAL – DO NOT COPY Page 9-22 File No. SG-0176...
  • Page 119 CH1 GPIO (R3); CH2 ATSC-SW(R121) POWER OFF CONFIDENTIAL – DO NOT COPY Page 9-23 File No. SG-0176...
  • Page 120: Trouble Shooting

    Chapter 10 Trouble shooting MONITOR DISPLAY NOTHING (PC MODE) Start Is Power board output +5V? LED is lighted Is J1 connector good? Is DC-DC OK? Is U4 (3.3V) working ok? It is in power saving Check video cable Is the timing supported? LED is lighting? Check sync input Check VGASOG rout if analog...
  • Page 121 (TV, COMPOSITE VIDEO1, 2, 3, S-VIDEO) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check DVD player 1.Check P2 signal 2.Check signal between P2 and U20 (IF AV1/AV2 mode) U20 input correct? 3.Check Tuner &U20 (IF TV mode) 4.Check J4&J6 (IF AV3&S-Video) 5.Check U20 POWER +9V 6.Check U22 data input/output...
  • Page 122 (COMPONENT1, 2) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check host’s setting 1.Check signal between P8&U21 U21 input correct? 2.Check U21 power 3.3V 1.Check signal between U21&U9 U9 input correct? 2.Check U9 Clock (27MHZ) 1.Check U9 2.Check U9 power 3.3V 1.8V LVDS output correct ? 1.Is J6 connected good? 2.Is panel working ok?
  • Page 123 HDMI ) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check host’s setting 1.Check p1 connect U16 input correct? 2.Check signal between P1 and 1.Check U16 power U16 no data out ? 2.Check between signal U16 and 3.Check clock 28.224MHZ 1.Is J6 connected good? 2.Is panel working ok? CONFIDENTIAL –...
  • Page 124 TROUBLE OF DC-DC CONVERTER Start The voltage is about + 5V 1.Check power board J1 PIN 9,10,11 2.Check power cable connection The voltage is about + 12V while power switch on J1 PIN 2,3,4,5 1.J1 connection good 2.Check U9 GPIO Pin 3.Check power board The voltage is about +5V while power switch on...
  • Page 125 TROUBLE OF DDC READING Start Support DDC1/2B 1.Analog cable ok? 2.Check signal (U18 to P3) Analog DDC OK? 3.Check U18 Voltage 4.Is compliant protocol? Support DDC1/2B 1.Analog cable ok? 2.Check signal (U17 to P1) HDMIDDC OK? 3.Check U17 Voltage 4.Is compliant protocol? CONFIDENTIAL –...

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