4-6. Ic Pin Function Description - Sony ICF-M33RDS Service Manual

Ver 1.1 2000. 01

4-6. IC PIN FUNCTION DESCRIPTION

• KEY BOARD IC101 µPD753012AGC-F05-3B9 (SYSTEM CONTROLLER, LCD DRIVER, KEY CONTROL)
Pin No. Pin Name
1 to 20 LCD12 to LCD31
21 to 24 COM0 to COM3
25 BIAS
26 VLCD0
27, 28 VLCD1, VLCD2
29 to 32 KS0 to KS3
33 VSS
34, 35 LIGHT
36 POWER
37 FM
38 VDET1
39 CLK/RX
40 DTA/RX
41 AF AUTO
42 TEST
43 CLK/RDS
44 DTA/RDS
45 SD
46 BUZZER
47 DTA/PLL
48 LAT/PLL
49 CLK/PLL
50 LAT/RX
51 HALT
52 KEYTEST
53 MUTE
54 VDD
55 XT1
56 XT2
57 IC
58 X1
59 X2
60 SFT CLK
61 PS MODE
62 to 67 KR0 to KR5
68 RESET
69 to 80 LCD0 to LCD11
I/O
O
Segment drive signal output to the liquid crystal display (LCD101)
O
Common drive signal output to the liquid crystal display (LCD101)
O
Liquid crystal display drive bias control output terminal Not used (open)
I
Develop liquid crystal display drive voltage input terminal
I
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
O
Key scan signal output of the key matrix (S102 to S117)
— Ground terminal
O
Liquid crystal display back light LED drive signal output terminal "L": back light on
O
PLL low-pass filter power supply on/off control signal output terminal "L": power on
O
RDS decode circuit power supply on/off control signal output terminal "L": power on
I Battery voltage detect signal input terminal "L" is input at low voltage
O
Clock signal output for the receive level control Not used (open)
O
Data output for the receive level control Not used (open)
AF mode selection signal input terminal "L": manual mode, "H": auto mode
I
Fixed at "L" in this set
I
Test mode input terminal "L": test mode Not used (open)
I Serial data transfer clock signal input from the RDS decoder (IC3)
I
Serial data input from the RDS decoder (IC3)
Station detector detect input from the CXA1019M (IC1)
I
Stop level for SEEK, BTM, etc. is determined SD is present at input of "L"
O
Beep sound drive signal output to the CXA1019M (IC1)
O
Serial data output to the FM/AM PLL (IC2)
O Serial data latch pulse signal output to the FM/AM PLL (IC2)
O
Serial data transfer clock signal output to the FM/AM PLL (IC2)
O
Latch signal output for the receive level control Not used (open)
O
"H" is output at halt mode Not used (open)
O "L" is output at test mode
O
Muting on/off control signal output terminal "L": muting on
—
Power supply terminal (+3V)
I
Main system clock input terminal (4.332 MHz)
O
Main system clock output terminal (4.332 MHz)
—
Connected to power supply (+3V)
I
Sub system clock input terminal (32.768 kHz)
O Sub system clock output terminal (32.768 kHz)
O
Alert signal output for the shift clock circuit "L": on, "H": off Not used (open)
I
Station name switch (S101) input terminal "L": station, "H": clock
I
Key return signal input of the key matrix (S102 to S117)
System reset signal input from the reset signal generator (IC103) "L": reset
I
"L" is input for several 100 msec after power on, then it changes to "H"
O
Segment drive signal output to the liquid crystal display (LCD101)
Description
– 28 –