Ic402: 16M Sdram (Em636165Ts-7 Etc) - Marantz SA-11S1 Service Manual

IC402: 16M SDRAM (EM636165TS-7 etc)

Terminal Function
Pin No. Pin Name
1 V
DD
2 DQ
0
3 DQ
1
4 V
SSQ
5 DQ
2
6 DQ
3
7 V
DDQ
8 DQ
4
9 DQ
5
10 V
SSQ
11 DQ
6
12 DQ
7
13 V
DDQ
14 L DQM
15 WE
16 CAS
17 RAS
18 CS
19 BA
20 A /AP
10
21 A
0
22 A
1
23 A
2
24 A
3
25 V
DD
26 V
SS
27 A
4
28 A
5
29 A
6
30 A
7
31 A
8
32 A
9
33 N. C
34 CKE
35 CLK
36 U DQM
37 N. C/RFU
38 V
DDQ
39 DQ
8
40 DQ
9
41 V
SSQ
42 DQ
10
43 DQ
11
44 V
DDQ
45 DQ
12
46 DQ
13
47 V
SSQ
48 DQ
14
49 DQ
15
50 V
SS
Symbol
Power Supply/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output Mask
Write Enable
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select Address
Address
Address
Address
Address
Address
Power Supply/Ground
Power Supply/Ground
Address
Address
Address
Address
Address
Address
No Connection
Clock Enable
System Clock
Data Input/Output Mask
NC/Reserved
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Data Output Power/Ground
Data Input/Output
Data Input/Output
Power Supply/Ground
Power and ground for the input buffer and the core logic
Data input/output are mutiplexed on the same pin
Data input/output are mutiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are mutiplexed on the same pin
Data input/output are mutiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are mutiplexed on the same pin
Data input/output are mutiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are multiplexed on the same pin
Data input/output are multiplexed on the same pin
Isolated power supply and ground for the output buffer
Blocks data input when active
Enables write operation and row precharge
Latches column address on the positive going edge of the CLK at low
Latches row address on the positive going edge of the CLK at low
Disables or enables device operation by masking or enabling all
inputs except CLK, CKE, and LDQM
Selects bank to be activated during row address latch time
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Power and ground for the input buffer and the core logic
Power and ground for the input buffer and the core logic
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
Row/column addresses are multiplexed on the same pin
No connect pin
Masks system clock to freeze operation from the next clock cycle
Active on the positive going edge to sample all inputs
Blocks data input when active
No connect pin
Isolated power supply and ground for the output buffer
Data input/output are multiplexed on the same pin
Data input/output are multiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are multiplexed on the same pin
Data input/output are multiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are multiplexed on the same pin
Data input/output are multiplexed on the same pin
Isolated power supply and ground for the output buffer
Data input/output are multiplexed on the same pin
Data input/output are multiplexed on the same pin
Power and ground for the input buffer and the core logic
3-16
Function