TMC TI7NBA User Manual page 48

Chapter 6 BIOS and System Setup
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to retain
data.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
Bank DRAM Timing
These fields define the speed of the DRAM memory onboard. The
options are Normal, Medium, Fast, Turbo, SDRAM 8ns and
SDRAM10ns. By default, these fields are set to SDRAM 10ns.
DRAM Clock
The DRAM Clock can be set to Host CLK or the CPU clock itself and to
66MHz. By default, this field is set to Host CLK.
SDRAM Precharge Control
This field enables of enables the SDRAM Precharge Control.
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is 3.
Memory Hole
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to Disabled.
Read Around Write
DRAM optimization feature: If a memory read is addressed to a location
whose latest write is being held in a buffer before being written to
memory, the read is satisfied through the buffer contents, and the read is
not sent to the DRAM. The default setting is Enabled.
Concurrent PCI/Host
This field enables or disables the concurrent PCI/Host. The default
setting is Disabled.
42 TI7NBA Socket 370 ATX Motherboard User's Manual