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HP 5300 Reviewer's Manual: Architecture; Hardware Architecture Summary; N-chip

Procurve 5300xl series.
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2.1.9 New Features in Software Release E.07.21
ACLs
SSHv2
IGMPv3
Debug/Logging

2.2 Architecture

2.2.1 Hardware Architecture Summary
The HP ProCurve Switch 5304xl has 4 identical slots, while the HP ProCurve Switch 5308xl has eight.
Any of the Switch 5300xl modules can be put in any of the slots.
The switch architecture is based on 2 different HP designed ASICs: the Network or N-Chip, and the
Fabric or F-Chip. Each module has an N-Chip that provides on-module routing and switching functions.
It also provides the high speed connection to the backplane. The F-Chip, located on the backplane,
provides the wire speed crossbar fabric interconnecting all the modules. This combination of highly
integrated N-Chips connected through the F-Chip gives the HP ProCurve Switch 5300xl Series the
ability to deliver wire-speed Layer 3 for the price of Layer 2 switching, and in a chassis form factor.
Table Memory
Table Memory
Input Memory
Input Memory
Output Memory
Output Memory
The HP ProCurve Switch 5300xl Series have two slots in the back for the load-sharing power supplies.
One power supply ships standard with each switch and can power a fully loaded chassis. A second
power supply can be installed for redundancy and longer overall expected power supply life.
The HP ProCurve Switch 5300xl Series can hold up to 16,536 (16K) MAC addresses in the switch
address table.
2.2.2 N-Chip
Each module contains a full ASIC-based Layer 3 routing switch engine. This switch engine, called the
network or N-Chip, provides all the packet processing: Layer 2 and Layer 3 lookups, filtering and
forwarding decisions, VLAN, trunking and priority queuing determinations. The N-Chip also contains
its own CPU.
© Hewlett-Packard Co. 2002, 2003
HP ProCurve Switch 5300xl Series Reviewer's Guide
XRRP
SSL
Meshing improvements
Management
CPU
Subsystem
9.6 Gbps
backplane link
N-Chip
Fabric Interface
CPU
Programmable
Look-up
Memory
Classifier
Subsystem
24 10/100 MACs
4 GbE MACs
...
Figure 1. Detailed Architecture
Rev 1.1 – 2/11/2003
http://www.hp.com/go/hpprocurve
(released January 22, 2003)
F-Chip
CPU Interface
Cross Bar Fabric
Fabric Buffer
8 Fabric Ports
Table Memory
Table Memory
Input Memory
Input Memory
Output Memory
Output Memory
100FX module software support
SNMPv3
OSPF Route Authentication
N-Chip
Fabric Interface
CPU
Programmable
Look-up
Memory
Classifier
Subsystem
24 10/100 MACs
4 GbE MACs
Page 11 of 35

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