LG 42PG20 Training Manual page 34

Plasma display panel
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CIRCUIT DeSCRIPTIONS
Y-SUS blOCk DIAGRAM
4
Z SUS Section on the
Same PWB
2
P
G
Left/Right X Board
2
0
Y-SUS P101 TO CONTROl P160
These connector pins are too close to read
without possible damage to the board. It's a
60 Pin connector but only has labels 1-19
on the Control board. Looking closely, these
test points are "every other pin". The bottom
TP represents the "19" label on the Control
board. Pin 1 on the Y-Sus board is actually pin
60 on the Control board side. Take resistance
readings with the board disconnected using the
Diode mode on a digital volt meter. However,
this connector has many more pins than shown
on the Control board Labeling. Roughly 39 pins
34
PDP Training - Fall 2008
Power Supply Board - SMPS
Distributes 5V VS
Receive 5V VCC, Va, Vs
Distributes 16V VA
Circuits generate
Y Sustain Waveform
FETs amplify Sustain
Waveform
Transfer Waveform
to Y Drive Board
Distributes 5V
from SMPS
Generates Vsc, -Vy and V Set Up
from Vs by DC/DC Converters
Y-Sus P101
Control Board
generate drive
Display Panel
Logic signals
needed to
waveform

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