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LG 42PG20 Training Manual
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LG 42PG20 Training Manual

LG 42PG20 Training Manual

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Download this manual See also: Owner's Manual
Training Manual
42PG20 Plasma Display
42PG20 Plasma Display
Advanced Single Scan Troubleshooting
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Summary of Contents for LG 42PG20

  • Page 1 Training Manual 42PG20 Plasma Display 42PG20 Plasma Display Advanced Single Scan Troubleshooting 720p 720p...
  • Page 2 • Y Drive Boards (Receives Y Drive signals from Y-SUS PWB) • Z SUS Output Board (Receives Z SUS signals from Y-SUS PWB) • Control Board (Outputs Y and Z control signals to Y SUS PWB) • X Drive Boards (2) • Main Board Plasma Fall 2008 42PG20...
  • Page 3 This Section will get the Technician familiar with the Disassembly, Identification and Layout of the Plasma Display Panel. At the end of this Section the Technician should be able to Identify the Circuit Boards and have the ability and knowledge necessary to safely remove and replace any Circuit Board or Assembly. Plasma Fall 2008 42PG20...

  • Page 4: Important Safety Notice

    When servicing this product, under no circumstances should the original design be modified or altered without permission from LG Electronics. Unauthorized modifications will not only void the warranty, but may lead to property damage or user injury.

  • Page 5: Regulatory Information

    Increase the separation between the equipment and the receiver; Connect the equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the dealer or an experienced radio/TV technician for help. Plasma Fall 2008 42PG20...
  • Page 6 USA Website (GCSC) aic.lgservice.com Customer Service Website us.lgservice.com LG CS Academy lgcsacademy.com LG Web Training lge.webex.com Published March 2009 by LG Technical Support and Training LG Electronics Alabama, Inc. 201 James Record Road, Huntsville, AL, 35813. Plasma Fall 2008 42PG20...
  • Page 7 1. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy. 2. Check the model label. Verify model names and board model matches. 3. Check details of defective condition and history. Example: Y Board Failure, Mal-discharge on screen, etc. Plasma Fall 2008 42PG20...
  • Page 8 The final step is to correct the problem. Be careful of ESD and make sure to check the DC Supplies for proper levels. Make all necessary adjustments and lastly always perform a Safety AC Leakage Test before returning the product back to the Customer. Plasma Fall 2008 42PG20...
  • Page 9 42PG20 Product Information 42PG20 Product Information This section of the manual will discuss the specifications of the 42PG20 Advanced Single Scan Plasma Display Panel. Plasma Fall 2008 42PG20...
  • Page 10 • Fluid Motion • 3x HDMI™ V.1.3 with Deep Color • AV Mode (Cinema, Sports, Game) • Clear Voice • LG SimpLink™ Connectivity • Invisible Speaker System • 100,000 Hours to Half Brightness (Typical) • PC Input Plasma Fall 2008 42PG20...
  • Page 11 42PG20 Specifications Logo Familiarization 42PG20 Specifications Logo Familiarization HD RESOLUTION 720p HD Resolution Pixels: 1365 (H) × 768 (V) High definition television is the highest performance segment of the DTV system used in the US. It’s a wide screen, high-resolution video image, coupled with multi-channel, compact-disc quality sound.
  • Page 12 10.2Gbps) than that of HDMI 1.2, delivering a broader range of colors, and also drastically improves the data-transmission speed. LG SIMPLINK™ MULTI-DEVICE CONTROL Allows for convenient control of other LG SimpLink products using the existing HDMI connection. Dual XD Engine...
  • Page 13 42PG20 Specifications Logo Familiarization 42PG20 Specifications Logo Familiarization AV Mode "One click" - Cinema, Sports, Game mode. TAKE IT TO THE EDGE is a true multimedia TV with an AV Mode which allows you to choose from 3 different modes of Movies, Video Games and Sports by a single click of a remote control.
  • Page 14 Digital is the reigning standard for surround sound technology in general and 5.1-channel surround sound in particular. Invisible Speaker Personally tuned by Mr. Mark Levinson for LG TAKE IT TO THE EDGE newly introduces ‘Invisible Speaker’ system, guaranteeing first class audio quality personally tuned by Mr. Mark Levinson, world renowned as an audio authority.
  • Page 15 60Hz Moving Picture Response Time Moving Picture Response Time is 16.5 milliseconds is 5.44 milliseconds (120Hz takes MPRT to 8.25ms) Panel Response Time Panel Response Time is less than 1 millisecond is 4 to 8 milliseconds Plasma Fall 2008 42PG20...
  • Page 16 42PG20 Remote Control 42PG20 Remote Control TOP PORTION BOTTOM PORTION Plasma Fall 2008 42PG20...
  • Page 17 Rear Input Jacks Rear Input Jacks Plasma Fall 2008 42PG20...
  • Page 18 42PG20 Dimensions 42PG20 Dimensions Plasma Fall 2008 42PG20...
  • Page 19 DISASSEMBLY SECTION This section of the manual will discuss Disassembly, Layout and Circuit Board Identification, of the 42PG20 Advanced Single Scan Plasma Display Panel. Upon completion of this section the Technician will have a better understanding of the disassembly procedures, the layout of the printed circuit boards and be able to identify each board.
  • Page 20 42PG20 Removing the Back Cover 42PG20 Removing the Back Cover To remove the back cover, remove the 26 screws (The Stand does not need to be removed). Indicated by the arrows. PAY CLOSE ATTENTION TO THE TYPE, SIZE AND LENGTH Of the screws when replacing the back cover.
  • Page 21 42PG20 Circuit Board Layout 42PG20 Circuit Board Layout Panel ID Label Panel Voltage Label Y Drive Power Supply Y SUS & Z-SUS Drive Z-SUS Z drive from Y SUS Main “Digital” Control “Logic” Side Input (part main) Heat Sink Right “X”...
  • Page 22 Disconnect the following connectors: P201, P801, P101, P202 Remove the 3 screws holding the PWB in place Remove the PWB by lifting slightly and sliding the PWB to the left unseating P204 and P200 from the Y-SUS PWB Plasma Fall 2008 42PG20...
  • Page 23 Remove the PWBs. Control Button PWB Removal Disconnect the single connector P101. Remove the 2 screws holding the PWB in place Remove the PWB. (Note: Power PWB is behind the Control PWB. Remove it’s 2 screws and remove. Plasma Fall 2008 42PG20...
  • Page 24 HEAT SINK ). X-DRIVE PWBs REMOVAL: Disconnect all TCP ribbon cables from the defective X-Drive PWB. Remove the 5 screws holding the PWB in place. Remove the PWB. Reassemble in reverse order. Recheck Va/Vs/VScan/-VY/Z-Drive. Plasma Fall 2008 42PG20...
  • Page 25 Stand. Before an X Board can be removed the Heat Sink Assembly “F” must be removed. Y Drive Y and Z SUS Drive Power Supply Z-SUS Control “Logic” Main “Digital” Right “X” Left “X” Plasma Fall 2008 42PG20...
  • Page 26 P232 or P331 connectors mechanism upward Carefully lift the TCP ribbon up and off the Gently lift the locking mechanism upward on all cushion and out of the way. TCP connectors P201~206 or P301~306 Flexible ribbon cable Cushion Plasma Fall 2008 42PG20...
  • Page 27 Lift up the lock as shown by arrows. (The Lock can be easily broken. It needs to be handled carefully.) Pull TCP apart as shown by arrow. (TCP Film can be easily damaged. Handle with care.) Plasma Fall 2008 42PG20...
  • Page 28 Remove the 5 screws for either PWB or 9 total for both. (The Center screw secures both PWBs) Left X Board drives the right side of the screen Right X Board drive the left side of the screen Plasma Fall 2008 42PG20...
  • Page 29 Signal and Voltage Distribution Signal and Voltage Distribution SLIDE CORRECTED HANDOUT MANUAL ERROR Plasma Fall 2008 42PG20...
  • Page 30 At the end of this Section the technician should understand the operation of each circuit board and how to adjust the controls. The technician should be able with confidence to troubleshoot a circuit board failure, replace the defective circuit and perform all necessary adjustments. Plasma Fall 2008 42PG20...
  • Page 31 (4) Adjusting Voltage DC, Va, Vs (12) Model Name (5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb) (13) Max. Watt (Full White) (6) Trade name of LG Electronics (14) Max. Volts (7) Manufactured date (Year & Month) (15) Max. Amps...
  • Page 32 1) When the Y-SUS PWB is replaced 2) When a “Mal-Discharge” problem is encountered All label references are from a specific panel. 3) When an abnormal picture issues is encountered They are not the same for every panel encountered. Plasma Fall 2008 42PG20...
  • Page 33 Panel to Panel even in the same size category. • Set-Up and Ve are just for Label location identification and are not used with this panel. Manufacturer Bar Code Panel Vscan Z_BIAS “Rear View” Set-Up Plasma Fall 2008 42PG20...
  • Page 34 Check the sticker on the upper left side to confirm origin of the Panel or the White Label on the Power Supply itself to identify the PWB P/N. We will examine the Operation of the EAY43533901. Plasma Fall 2008 42PG20...
  • Page 35 Power Supply PWB Layout Power Supply PWB Layout P812 Hot Ground Symbol represents a SHOCK Hazard P813 16.5V 16.5V AC Det 5_V Det VS_ON RL_ON M5V_ON Plasma Fall 2008 42PG20...
  • Page 36 There are 2 adjustments located on the Power Supply Board VA and VS. The 5V VCC is pre-adjusted and fixed. All adjustments are made with relation to Chassis Ground. Use “Full White Raster” 100 IRE RV901 Adjustments RV951 Plasma Fall 2008 42PG20...
  • Page 37 VS Source 380V Source Circuit VA Source Standby VA VR901 Source 340V Fuse VS VR951 F801 10Amp/230V Main 16v, 5v Fuse Source F101 10Amp/230V P813 AC Input To MAIN CN 101 IC701 Sub Micon AC Input Plasma Fall 2008 42PG20...
  • Page 38 The last step to bring the supply to “Full Power” occurs when the Micon (IC100) on the Main Board brings the VS-ON line high at Pin 20 of P813 on the SMPS Board which when sensed by the Sub Micon IC (IC701) turns on the VA and VS Supplies (VA is brought high before VS). Plasma Fall 2008 42PG20...
  • Page 39 Audio would be present. If VS-ON went high and VS and VA where missing the problem could be caused by a failure on the SMPS or a circuit using these voltages. A Resistance check should narrow the possible failures quickly. Plasma Fall 2008 42PG20...
  • Page 40 Va routed to X-PWBs Stand Det. By 5V Note1 NOTE 1: Relay 50PG20 has 12V and 16V to Main at turn on. Det. 42PG20 only has 16V. Video Audio Turns on Red LED At point TV is in Relay Stand-By state.
  • Page 41 Microprocessor Side Microprocessor Side Control of the Switch Control of the Switch Mode Power Supply Mode Power Supply See next Slides Closer View Plasma Fall 2008 42PG20...
  • Page 42 Microprocessor Side Microprocessor Side Control of the SMPS Control of the SMPS Step 1 Step 1 Plasma Fall 2008 42PG20...
  • Page 43 Microprocessor Side Control of the SMPS Step 2 Microprocessor Side Control of the SMPS Step 2 Plasma Fall 2008 42PG20...
  • Page 44 For a “Stand-Alone” static test for the Power Supply, apply the usual 2 100Watt light Bulbs test on the Vs output line for a simulated load. If the Power Supply operates in this condition, it is assured it can maintain its output power under load. Plasma Fall 2008 42PG20...
  • Page 45 STATIC TEST UNDER LOAD LIGHT BULB TEST Plasma Fall 2008 42PG20...
  • Page 46 100Ω ¼ watt resistor added from 5V STB (Pins 9 ~ 12) to M5V_ ON (Pin 21) brings the 5V VCC line high 100Ω ¼ watt resistor added from 5V STB (Pins 9 ~ 12) to VS _ON (Pin 20) brings the VA and VS Lines high Plasma Fall 2008 42PG20...
  • Page 47 Supply will come Apply AC Power Generated “Yes” up and run with Power Supply Starts. “NO” load. P812 pulled. Vs TP Va TP P812 P812 Pin 1 or 2 Pin 5 or 6 Use Full White Raster Plasma Fall 2008 42PG20...
  • Page 48 480K 1 and 3 P812 CONNECTOR "Power Supply PWB“ to Y-SUS Label STBY Diode Mode *195V Open *195V Open *65V Open *65V Open 1.47V 1.37V * Note: This voltage will vary in accordance with Panel Label Plasma Fall 2008 42PG20...
  • Page 49 P813 CONNECTOR Odd "SMPS" to P701 "Main PWB" Label STBY No Load Diode Mode 16.5V 16.5V 1.5V Open 1.43V 1.43V 5_V Det .15V 1.92V RL_On 3.73V Open M5V_ON 3.24V Open Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 50 Voltage and Resistance Measurements for the SMPS (Page 2 of 2) P813 CONNECTOR Even "SMPS" to P701 "Main PWB" Label STBY No Load Diode Mode 16.5V 16.5V 1.5V Open 1.43V 1.43V AC Det 2.3V Vs_On 3.2V Open AUTO Open Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 51 Red and Blue. Relay clicks rapidly on and off. STBY 5V line toggles with relay from 2.2V to 5V. (4) 5Vcc Short: Power LED is lit Red in stand by. At Power On, goes to flashing Blue. 5Vcc line toggles rapidly between 0V to 0.7V. Plasma Fall 2008 42PG20...
  • Page 52 Ramp UP sets Pitch of the Top Ramp of the Drive Waveform V SET DN VR601 V Set Down sets the Pitch of the Bottom Ramp of the Drive Waveform VSC Set the amplitude of the complex waveform. To the X-Drives PWB and the TCP IC’s Plasma Fall 2008 42PG20...
  • Page 53 Generates Vsc and -Vy Circuits generate from Vs by DC/DC Converters Y Sustain Waveform Also controls Ramp Up/Down Left X Board Right X Board FETs amplify Sustain Waveform Transfer Waveform Display Panel to Y Drive Board Plasma Fall 2008 42PG20...
  • Page 54 P200 P801 Z-Bias ADJ VR905 ZBias TP R946 VSC ADJ VR501 Logic Signals P101 from the -VY ADJ VR502 Control PWB FS701 (Va) VSC TP 16V and Va to Left and R211 Right X PWBs P202 Plasma Fall 2008 42PG20...
  • Page 55 Voltage Adjustments Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash” mode or 100 IRE White input. Adjust –Vy to 190V (+/- 1V) Adjust VSC to 140 (+/- 1V) Plasma Fall 2008 42PG20...
  • Page 56 Y-Drive PWB Test Point Highlighted signal from figure above observed 100uS/div NOTE: If Vset DN too high, this set will go to excessive bright, then shutdown. To correct, remove the LVDS from control PWB and make necessary adjustments. Plasma Fall 2008 42PG20...
  • Page 57 Fig 3 Top: At 1ms per/div. the signal for Vsetup is now clearly visible. It is outlined within the Waveform FIG3 Area to be adjusted Zoomed out Fig 3 Lower: At 40uSec per/division, the adjustment for Vsetup can be made. Plasma Fall 2008 42PG20...
  • Page 58 Fig 1 Top: At 1ms per/div. the outlined signal for Vsetdn is now clearly visible. It is outlined within the Waveform FIG3 Fig 1 Lower: At 40uSec per/division, the adjustment for Vsetdn can be made. Area to be adjusted Zoomed out Plasma Fall 2008 42PG20...
  • Page 59 Set Down Adjustments Y SUSTAIN ADJUSTMENT DETAILS (Vs, Va, VSC, VSC, -Vy and Z-Bias Must have already been completed). Y-Drive PWB Test Point Observe the Picture while making these adjustments. Normally, they do not have to be done. Plasma Fall 2008 42PG20...
  • Page 60 Peeking too late and alters the start of the Vset DN phase. Ramp (Vset UP) too low Very little alteration to the picture, the wave form indicates a distorted Vset UP. The peek widens due to the Vset UP peeking too quickly. Plasma Fall 2008 42PG20...
  • Page 61 PWB and make necessary adjustments. Vset DN too high All of the center washes out due to increased Vset_DN time. Vset DN too low The center begins to wash out and arc due to decreased Vset DN time. Plasma Fall 2008 42PG20...
  • Page 62 NOTE: If Vset DN too high, this set will go to excessive bright, then shutdown. Notice that the amplitude of the Set To correct, remove the LVDS from Control PWB and Down (Bottom portion) peak begins to make necessary adjustments. decrease. Plasma Fall 2008 42PG20...
  • Page 63 Diode Mode *194V Open *194V Open *65V Open *65V Open .83V .83V * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected using the Diode mode on the DVM Plasma Fall 2008 42PG20...
  • Page 64 Open 61.5V Open 64.9V Open 15.8V 61.5V Open 61.5V Open *64.9V Open * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected using the Diode mode on the DVM Plasma Fall 2008 42PG20...
  • Page 65 ZSUS 70.46V Open ZSUS 70.46V Open ZSUS 70.46V Open ZSUS 70.46V Open * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected using the Diode mode on the DVM Plasma Fall 2008 42PG20...
  • Page 66 PWB Actually a 60 Pin Connector "Only Labels for 1-19" on the Control PWB Looking closely, these test points are “every other pin”. The bottom TP represents “19” label on the Control PWB. Plasma Fall 2008 42PG20...
  • Page 67 SET_UP 1.9V 2.87V Z-ER_UP 1.25V 1.1V SUS_UP 2.87V Set_DN_2 1.4V 2.87V Z-ER_DN 1.35V 1.1V ER_DN 1.2V 2.87V X_ER 2.9V 2.87V Z-SUS_UP 0.35V 1.1V ER_UP 2.87V Y-Enable 0.6V 2.87V Z-SUS_DN 1.15V 1.1V SET_UP 0.26V 2.87V 4.75V 0.76V Plasma Fall 2008 42PG20...
  • Page 68 Forward 0.5V ~ 0.7V Reverse: OL Reverse: OL RF2001 RF2001 Forward 0.3V ~ 0.5V Forward 0.3V ~ 0.5V Reverse: OL Reverse: OL 45F123 45F123 Forward 0.3V ~ 0.5V Forward 0.9V ~ 1.0V Reverse: OL Reverse: OL Plasma Fall 2008 42PG20...
  • Page 69 The Y Drive Boards supply a waveform which selects the horizontal electrodes sequentially. * 42PG20 uses 8 DRIVER ICs on 1 Y Drive Board Y DRIVE WAVEFORM To facilitate scope attachment, solder a small wire (Stand Off) at this point.
  • Page 70 Y Drive Sig Floating Ground from the Y SUS Board (Scan) BOTTOM Y-SUS SIDE P100 P200 PANEL SIDE Floating Ground from the Y SUS Board Check 5V supply using FL1 or C18. Measured from Floating Ground Plasma Fall 2008 42PG20...
  • Page 71 All voltages taken from Floating from Floating Ground. Ground. Warning: Do not Warning: Do not hook scope ground hook scope ground up unless set up unless set plugged into an plugged into an isolation isolation transformer. transformer. Plasma Fall 2008 42PG20...
  • Page 72 To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1). Plasma Fall 2008 42PG20...
  • Page 73 Note the cable is crooked. In this case the Tab on the Ribbon cable was improperly seated at the bottom. This can cause bars, lines, intermittent lines abnormalities in the picture. Remove the ribbon cable and re-seat it correctly. Plasma Fall 2008 42PG20...
  • Page 74 OL Red on Osc1 DATA In 0.58V Black on LE OL Red on LE 0.60V Black on CLK OL Red on CLK 0.78V Black on DATA OL Red on DATA 0.50V Black on +5V OL Red on +5V Plasma Fall 2008 42PG20...
  • Page 75 BLACK LEAD ON RED LEAD ON “ANY” Floating BUFFER IC OUTPUT LUG. Ground READING “OPEN” Indicated by white outline • Any of these output lugs can be tested. • Look for shorts indicating a defective Buffer IC Plasma Fall 2008 42PG20...
  • Page 76 Locations Locations • DC Voltage and Waveform Test Points • Z BIAS Alignment • Resistance Test Points Operating Voltages Operating Voltages Y SUS Supplied 5V Vcc Developed on Y SUS Z Bias Plasma Fall 2008 42PG20...
  • Page 77 Z SUS Z-Bias ADJ VR905 Section Z Drive to Z SUS P801 Output PWB VZ (Z-Bias) TP R946 Logic Signals from the Control PWB P101 FS701 (Va) P202 16V and Va to Left and Right X PWBs Plasma Fall 2008 42PG20...
  • Page 78 Note: The Vzb + - 1V 100V bottom leg of R1 to check Z Adjustment is a Output waveform DC level adjustment 100uS/div This Waveform is just for reference to observe the effects of Zbz adjustment Plasma Fall 2008 42PG20...
  • Page 79 P801 Z-SUS VZ (Z-Bias) TP R946 Set should run for 15 minutes, this is the “Heat Run” mode. Set screen to “White Wash” mode or 100 IRE White input. Adjust VZ (Z-Bias) to 100V (+/- 1V Plasma Fall 2008 42PG20...
  • Page 80 Input Voltages from the Y SUS Board VS is input at P1 pin 1 and supplied to the FETs. Input Signals from the Y SUS Board Input Signals from the Y SUS Board Z Drive Signals to Power FET’s Plasma Fall 2008 42PG20...
  • Page 81 Distributes Logic Signals VS, VA, M5V Control Board Circuits generate erase, Generates Z Bias 100V sustain waveforms Z-SUS PWB Display Panel FET Makes Drive waveform Z-SUS FETs Via FPC Via P801 to P1 (flexible printed circuit ) Plasma Fall 2008 42PG20...
  • Page 82 Diode Mode *194V Open ZSUS 70.46V Open ZSUS 70.46V Open ZSUS 70.46V Open ZSUS 70.46V Open ZSUS 70.46V Open * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 83 • DC Voltage and Waveform Test Points • Resistance Test Points Signals Signals Main Board Supplied LVDS Signal Operating Voltages Operating Voltages Y SUS Supplied 5V VCC Developed on the 1.8V Control board (2) 3.3V Plasma Fall 2008 42PG20...
  • Page 84 Y-Z- IC211 P160 IC213 To P101 Y-SUS AUTO GEN TEST IC171 PATTERN IC122 3.3V IC171 Part Number Pin 1 ---- 3.29V Label Pin2 ---- 1.20v 3.3V Pin 3 ---- 0V P161 P162 To X Drive Left Plasma Fall 2008 42PG20...
  • Page 85 Control PWB Pictorial IC121 Pin 1 – 4.75V Pin 2 – 3.3V Pin 3 – 0V Note: P812 on SMPS P201 on Y SUS IC122 Pin 1 – 4.75V Pin 2 – 3.3V Pin 3 – 0V Plasma Fall 2008 42PG20...
  • Page 86 If there is a picture of cycling colors, the Y-SUS, Y-Drive, Z-SUS, Power Supply, Control PWBs and Panel are all OK. Same test for (2) to tell if the No Video is caused by the Main PWB. Plasma Fall 2008 42PG20...
  • Page 87 ” DC Voltage Check 1.5V ~ 1.8V Osc. Check: 50Mhz Check the output of the Oscillator package. The frequency of the sine wave is 50 MHZ. Missing this clock signal can halt operation of the unit Plasma Fall 2008 42PG20...
  • Page 88 Menu Button “on” and “off” with the Remote Control or Keypad. Loss of these Signals would confirm the failure is on the Main Board! Menu ON Menu Off Example of Normal Signals measured at 200mv/cm at 5µs/cm. Plasma Fall 2008 42PG20...
  • Page 89 CONTROL PWB EEPROM DRAM X-DRIVE PWB Resistor Array DRAM DRAM 16 line 2 Buffer PANEL Outputs per TCP 96 Lines per Buffer 192 Lines output Total Plasma Fall 2008 42PG20...
  • Page 90 Removing the LVDS Cable from the Control PWB The LVDS Cable has two “Interlocks” that must be disengaged to remove the LVDS Cable. To Disengage, press the two Locking Tabs Inward and pull the plug out. Press Press Inward Inward Plasma Fall 2008 42PG20...
  • Page 91 P121 CONNECTOR Even Pins "Control” to P302 “Main” Diode Mode Diode Mode 1.26V 1.19V 1.26V 1.19V 1.15V 1.26V 0.21V 0.89V 0.56V 2.5V 5.29V 2.4V 1.26V 1.2V 3.29V 1.3V 0.89V 3.29V Open 0.89V 3.29V Open Open Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 92 39 Pins related to Y-SUS Actual Pin 1 (ground) 2 (Z-SUS- DN) 3 (ground) 4 (Z-SUS-UP) 5 (ground), etc…. In other words, there is a ground between each pin except the +5V area. Plasma Fall 2008 42PG20...
  • Page 93 1.34V Z-ENABLE 1.31V OSC1 1.34V DELTA_Vy 0.16V 1.34V 0.76V 1.34V 4.75V 1.06V PASS_TOP 0.2V 1.34V 4.75V 1.06V 4.75V 1.06V 3.2V 1.34V Set_DN2 0.2V 1.34V 4.75V 1.06V (All 5V Lines 17~21 Resistance in Ohms readings are 1.7K) Plasma Fall 2008 42PG20...
  • Page 94 Voltage and Resistance Measurements can’t be made. P161 CONNECTOR "Control PWB" to "X Drive Left" P232 These pins are covered in silicon P162 CONNECTOR "Control PWB" to "X Drive Right" P331 These pins are covered in silicon Plasma Fall 2008 42PG20...
  • Page 95 B/D measurements can ’ t be made. Between Ctrl. B/D and X B/D measurements can ’ t be made. Signal cable P161 P161 P162 P162 P232 P331 P232 P331 P211 P211 P311 P311 Power Cables (Va, 15V) Plasma Fall 2008 42PG20...
  • Page 96 Developed on the X-Drive boards: VPP to help with over all current draw during “No Video” times when the panel is being driven. VPP shuts off the TCPs during this time. VPP is generated using Va and a drive signal from the Control board. Plasma Fall 2008 42PG20...
  • Page 97 Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed. After a very short time, these ICs will begin to self destruct due to overheating. TCP IC TCP IC TCP IC’s shown are part of the Ribbon Cable Plasma Fall 2008 42PG20...
  • Page 98 Carrier Carrier TCP (Tape TCP (Tape Package) Package) Plasma Fall 2008 42PG20...
  • Page 99 TCP ICs receive RGB 16 bit signal to the PDP by connecting the PAD Electrode of the PANEL with the X Board. To Panel Y-SUS PWB Va and 16V Control PWB Connector Back side of Ribbon Connector into X-Drive Plasma Fall 2008 42PG20...
  • Page 100 TCP Testing TCP Testing On any Gnd 10,11,12,13,14,27,28,2 9,30,37,38,39,40,41 Look for any TCPs being On any Va discolored. 4,5,6,7,44,45,46,47 Ribbon Damage. Cracks, folds Pinches, scratches, etc… Typical Reading 0.65V Opposite reads open Plasma Fall 2008 42PG20...
  • Page 101 Generate abnormal vertical bars c) Cause the entire area driven by the TCP to be “All White” d) Cause the entire area driven by the TCP to be “All Black” e) Cause a “Single Line” defect Plasma Fall 2008 42PG20...
  • Page 102 P211 CONNECTOR "X Drive Left" to "Y-SUS" P202 Label STBY Diode Mode 15.4V Open VPP/ER1 *61.4V Open VPP/ER1 *61.4V Open *64.9V Open * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 103 P311 CONNECTOR "X Drive Right" to "Y-SUS" P202 Label STBY Diode Mode Open VPP/ER2 *61.4V Open VPP/ER2 *61.4V Open *64.9V Open * Note: This voltage will vary in accordance with Panel Label Resistance Readings with the PCB Disconnected Plasma Fall 2008 42PG20...
  • Page 104 Voltage and Resistance Measurements for these connectors are difficult to read. They are too close together for safe test. The pins are also protected by a layer of tape to prevent the tab from being released causing separation from the Cable and the connector. Plasma Fall 2008 42PG20...
  • Page 105 • DC Voltage and Waveform Checks • Resistance Measurements SMPS Supplied Operating Voltages Operating Voltages Developed on the Main 3.3V (2) Board 2.5V 1.8V Plasma Fall 2008 42PG20...
  • Page 106 IC100 X400 Tuner Pin 1 Microprocessor 25 Mhz LD703 HDMI 3 X100 12 Mhz To Front Audio RGB/DVI Controls RS232 RGB/PC P303 Remote SPK Out Optical Audio JK501 Audio Component inputs A/V Composite inputs HDMI inputs Plasma Fall 2008 42PG20...
  • Page 107 IC709 3.29V 1.26V IC501 MAIN PWB Location BACK SIDE Be sure to prevent the PWB from touching the frame VIEW while the PWB is turned over. IC805 Use a piece of cardboard or towel to insulate. Plasma Fall 2008 42PG20...
  • Page 108 Main PWB Tuner Check (Shield Off) Pins Exposed LD400 Tuner Osc. VIF Pin 16 Video Test Point Lock On Unlocked SIF Pin 14 Audio Test Point Off Locked IC400 Tuner Controller Pin 3 Tuner B+ (5V) X400 Tuner Controller Osc. Plasma Fall 2008 42PG20...
  • Page 109 Main PWB Tuner Video and SIF Output Check Main PWB Tuner Video and SIF Output Check USING COLOR BAR SIGNAL INPUT Pin 14 “SIF” Signal 850mVp/p 20nSec rate Pin 16 “Video” Signal MAIN 1Vp/p 20uSec rate Tuner Location Plasma Fall 2008 42PG20...
  • Page 110 1.25V 1.17V 1.21V 1.17V 1.27V 1.17V 1.25V 1.17V 1.22V 1.17V 1.21V 1.17V 1.24V 1.17V 1.18V 1.17V 1.24V 0.83V 0.93V 3.29V 1.5V 0.58V 1.01V 3.29V Open Resistance Readings with the PWB Disconnected. DVM in the Diode mode. Plasma Fall 2008 42PG20...
  • Page 111 Voltage and Resistance Measurements for the Main Board P303 CONNECTOR "MAIN PWB" to "Front Keys" STBY Diode Mode 2.99V 3.29V 1.18V 3.29V 1.18V 0.75V 1.12V 3.84V 1.03V Resistance Readings with the PCB Disconnected. DVM in the Diode mode. Plasma Fall 2008 42PG20...
  • Page 112 P701 CONNECTOR "Main" Odd Pins to "SMPS PWB" P813 Label STBY Diode Mode 16.5V 3.8V Open 0.75V 0.75V 5_V Det .15V 3.25V RL_On 3.73V Open M5V_ON 3.24V 1.22V Resistance Readings with the PWB Disconnected. DVM in the Diode mode. Plasma Fall 2008 42PG20...
  • Page 113 P701 CONNECTOR "Main" Even Pins to "SMPS PWB" P813 Label STBY Diode Mode 16.5V 2.82V Open 0.75V 0.75V AC Det Open Vs_On 3.2V 1.22V AUTO Resistance Readings with the PWB Disconnected. DVM in the Diode mode. Plasma Fall 2008 42PG20...
  • Page 114 Main PWB Speaker Plug JK501 Voltages and Resistance Voltage and Resistance Measurements for the Main Board Speaker Plug CN701 CONNECTOR "Main" to "Speakers" Diode Mode 2.58V 2.58V 2.58V 2.58V JK501 Resistance Readings with the PWB Disconnected. DVM in the Diode mode. Plasma Fall 2008 42PG20...
  • Page 115 To remove, unplug the connector P101 and remove the 2 screws. Under each screw there is a black tab. Release these tabs to lift the PWB upward. Then remove the connector from the Power Switch PWB and remove it’s two screws. Plasma Fall 2008 42PG20...
  • Page 116 BLOCK DIAGRAMS SIGNAL PATH SECTION SECTION 4: BLOCK DIAGRAMS SIGNAL PATH SECTION The following section gives a block diagram and isolates the location related to different circuits related to signal flow. Use this block diagram to help isolate the problem. Plasma Fall 2008 42PG20...
  • Page 117 Block Diagram Analog and Digital Inputs Block Diagram Analog and Digital Inputs ATSC/NTSC Tuner Pin 16 Analog Video Pin11 Pins 10, 11 Digital Video Plasma Fall 2008 42PG20...
  • Page 118 (4) Examine Scan IC’s on Y Drive Boards use Diode Check No Reset (5) Check LVDS cable from Main to CTRL B/D, Short Pins of Test Pattern TP CTRL B/D Test Patterns Reset Occurs (6) Check VA to the X Boards Reset Occurs Plasma Fall 2008 42PG20...
  • Page 119 This fold out is provide as a Quick guide to troubleshooting tips giving through out this presentation. Special Note: This foldout has changed since the publication of the original Training Manual. Please use the information contained here instead of the original paper fold out. Plasma Fall 2008 42PG20...
  • Page 120 Y-SUS DRIVE WAVEFORM 42PG20 CIRCUIT INTERCONNECT DIAGRAM Z-SUS RAMP 150V To Peak See next page for Y-SUS TP waveforms VZ Bias P302 Remove all input signals State Ref# Z-SUS TP from the unit so the P812 P813 Menu Off menu will be the only...
  • Page 121 Time per division Trigger offset Volts per division Pin 22 - Menu off P302 P302 Pin 16 - Menu off Pin 12 - Menu off Pin 13 - Menu off Pin 19 - Menu off State State Ref # Ref # Menu Off Menu Off Menu On...

  • Page 122: Thank You

    End of Presentation End of Presentation This concludes the Presentation Thank You Plasma Fall 2008 42PG20...