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Sanyo DC-MP7500(BK)/(XE) Service Manual page 17

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IC BLOCK DIAGRAM & DESCRIPTION
IC441 TC9422F (Volume Control)
L-IN1
2
L-IN2
3
L-IN3
4
L-IN4
5
L-SW-OUT
6
7
L-VR-IN
L-B1
8
L-B2
9
10
L-B3
11
L-Tone-OUT
L-T1
12
IC601 PT6315 (VFD Driver / Controller IC)
7
DIN
Serial
6
DOUT
Data
CLK
8
Display Memory
Interface
(24 bits x 17 Words)
STB
9
TI~inc Generator
OSC
5
OSC
Key Moter Memory
1
LED1
LED
2
LED2
Driver
3
LED3
LED4
4
10
K1
GND
INPUT
SELECTOR
100k
GAIN CONTROL
0, 6, 12, 18dB
MAIN VR
50k / 64STEP
50k
CAPACITOR FOR
OSCILLATION
BASS VR
50k /
16STEP
500
13k
TREBLE VR
50k /
16STEP
750
50k
50k
13
Vref
Control
Driving Circuit
11
13
30
K2
VDD
GND
VEE
V
DD
1
28
GAIN CONTROL
0, 6, 12, 18dB
50k / 64STEP
BASS VR
50k /
16STEP
TREBLE VR
50k /
16STEP
32BIT SR
14
15
16
CK
DATA
STB
14
SG1/KS1
15
SG2/KS2
16
SG3/KS3
17
SG4/KS4
18
SG5/KS5
19
SG6/KS6
Segment
20
SG7/KS7
Driver
21
SG8/KS8
22
SG9/KS9
Grid
Driver
23
SG10/KS10
24
SG11/KS11
Key Scan
25
SG12/KS12
Output
26
SG13/KS13
27
SG14/KS14
28
SG15/KS15
30
SG16/KS16
31
SG17/GR12
32
SG18/GR11
33
SG19/GR10
34
SG20/GR9
35
SG21/GR8
36
SG22/GR7
37
SG23/GR6
38
SG24/GR5
42
GR1
41
GR2
Grid
Driver
40
GR3
39
GR4
- 16 -
INPUT
SELECTOR
100k
27
R-IN1
26
R-IN2
25
R-IN3
24
R-IN4
23
R-SW-OUT
MAIN VR
22
R-VR-IN
21
R-B1
50k
R-B2
20
19
R-B3
CAPACITOR FOR
OSCILLATION
18
R-Tone-OUT
500
13k
17
R-T1
750
Pin Name
I/O
Description
LED1 to LED4
O
LED Output Pin
Oscillator Input Pin
OSC
I
A resistor is connected to this pin to
determinc the oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
DOUT
O
This pin outputs scrial data at the falling
edge of the shift clock
(starting from the lower bit)
Data Input Pin
DIN
I
This pin inputs serial data at the rising edge
(Schmitt Trigger)
of the shift clock (starting from the lower bit)
Clock Input Pin
CLK
I
This pin reads serial data at the rising edge
(Schmitt Trigger)
and outputs data at the falling edge.
Serial Interface Strobe Pin
STB
The data input after the STB has fallen is
I
(Schmitt Trigger)
processed as a command.
When this pin "HIGH",CLK is ignored,
Key Data Input Pins
K1 to K2
I
The data inputted to these pins are fatched
at the end of the display cycle.
VSS
-
Logic Ground Pin
VDD
-
Logic Power Supply
High-Voltage Segment Output Pins
SG1/KS1 to
O
Also acts as the Key Source
SG16/KS16
-
Pull-Down Level
VEE
O
High Voltage Segment/Grid Output Pins
SG17/GR12 to
SG24/GR5
O
High-Voltage Grid Output Pins
GR4 to GR1
Pin No.
1 to 4
5
6
7
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42

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