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Sanyo DC-MP7500(BK)/(XE) Service Manual page 14

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IC BLOCK DIAGRAM & DESCRIPTION
IC160 ES3890F (VCD Processor)
SRAM/ROM
Interface
TDM
Transport
Interface
Parser
Serial Audio
Interface
Audio
ADC
Names
Pin No.
I/O
VSSA
1.9
G Ground for analog circuits.
Reset. Internal current source generator. Connect this pin to
RSET
2
O
a 510Ω resistor to ground.
Output reference voltage. Connect to a 0.01-µF high -frequency
VREF
3
O
bypass capacitor to VSSA.
Compensation capacitance for low-pass filter on VDAC. Connect
COMP
4
O
to a 0.01-µF high-frequency bypass capacitor to VSSA.
ADC analog voltage reference. Connect to a 0.01-µF filter
VCM
5
O
capacitor to VSSA.
MIC1.MIC.2
6,7
I
Microphone inputs.
VDDA
8
P 5.0V power supply for analog circuits.
AUX0[7:5]
10:12
I/O General-purpose programmable I/O.
AUX3[2:0]
13:15
I/O General-purpose programmable I/O.
LWR#
16
O RISC interface Write Enable (active-low).
LOE#
17
O RISC SRAM Output Enable (active-low).
CS0#
18
O Chip select 0 for SRAM (active-low).
CS1#
19
O Chip select 1 for SRAM (active-low).
CS3#
20
O Chip select 3 for SRAM (active-low).
LD[7:0]
21:28
I/O Data bus.
VCC
29.42.66.95.116
P Core power supply (2.5V).
XIN
30
I
Crystal connection or input source of 27MHz. Must be 50% duty cycle.
XOUT
31
O Crystal connection or output drive of an input clock source.
VSS
32,41,65,97,117
G Ground for core.
LA[19:0]
33:40,43:54
O Address bus.
TDMFS
55
I
Frame signal from CDROM.
TDMDR
56
I
Data signal from CDROM.
TDMCLK
57
I
Clock signal from CDROM.
TBCK
58
O Transmit clock when sending audio IIS data to external DAC.
PLL mode select 1. Pulldown to ground to bypass PLL. Pullup to
SEL_PLL1
I
59
VCC for optimal performance.
TWS
O Audio strobe signal of IIS signals to external DAC.
PLL mode select 0. Pulldown to GND to bypass PLL. Pullup to VCC
SEL_PLL0
I
60
for optimal performance.
TSD
O Audio data of IIS signals to external DAC.
Media clock input to drive external audio devices or media clock
MCLK
61
I/O
output when driven by external source into the ES 3890.
CAS#
62
O Column Address Strobe to DRAM (active-low).
DRAS1#
63
O Row Address Strobe 1 to DRAM (active-low).
VPP
64
P 5V power supply.
DRAS0#
67
O Row Address Strobe 0 to DRAM (active-low).
DWE#
68
O Write Enable to DRAM (active-low).
DOE#
O Data Out Enable to DRAM (active-low).
69
MA9
O Multiplexed memory row and column address.
MA[8:0]
70:78
O Multiplexed memory row and column address.
IC190 M11L16161SA-45T (DRAM)
V
V
1
50
CC
SS
I/O1
I/O16
2
49
I/O2
I/O15
3
48
I/O3
I/O14
4
47
I/O4
I/O13
5
46
V
V
6
45
CC
SS
I/O5
I/O12
7
44
I/O6
I/O11
8
43
I/O7
I/O10
9
42
I/O8
I/O9
10
41
NC
NC
11
40
NC
NC
15
36
NC
LCAS
16
35
WE
UCAS
17
34
RAS
OE
18
33
NC
A9
19
32
NC
A8
20
31
A0
A7
21
30
A1
A6
22
29
A2
A5
23
28
A3
A4
24
27
V
V
25
26
CC
SS
GPIO
TV-Encoder
Interface
32-bit
OSD
RISC Processor
Display
Controller
8kB cache
Gateway
DMA Controller
Huffman
DRAM
Decoder
Interface
Video
Processor
Descriptions
PIN NO.
PIN NAME
21-24, 27-32
A0-A9
18
RAS
34
UCAS
35
LCAS
17
WE
33
OE
2-5, 7-10, 41-44, 46-49
I/O1 - I/O16
1, 6, 25
VCC
26, 45, 50
VSS
11, 15, 16, 36, 40
NC
- 13 -
128
VSSA
RSEVT
VREF
COMP
VCM
MIC2
MIC1
VDDA
VSSA
AUX0[5]
AUX0[6]
AUX0[7]
AUX3[0]
AUX3[1]
AUX3[2]
LWR#
LOE#
CS0#
CS1#
CS3#
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
VCC
XIN
XOUT
VSS
LA0
LA1
LA2
LA3
LA4
38 39
LA5
Names
Pin No.
I/O
DBUS[15:0]
79:94
I/O Input when DRAM is being read. Output when DRAM is being written.
REST#
96
I
External system reset forces ES3890 to do a reset (active-low).
VSS_P
98
G Ground for system PLL.
VCC_P
99
P 2.5V power supply for system PLL.
AUX2[0]
I/O General-purpose programmable I/O.
100
VFD_CLK
I
VFD clock
AUX2[1]
I/O General-purpose programmable I/O.
101
SQSO
I
Subcode-Q data.
AUX2[2]
I/O General-purpose programmable I/O.
102
SQCK
I
Subcode-Q clock.
AUX2[3]
103
I/O General-purpose programmable I/O.
AUX2[4]
I/O General-purpose programmable I/O.
104
C2PO
I
C2PO error correction flag from CDROM.
AUX2[5]
I/O General-purpose programmable I/O.
105
SP
I
Serial port from 16550 UART.
AUX2[6]
I/O General-purpose programmable I/O.
106
S0S1
I
Subcode-Q sync.
AUX2[7]
107
I/O General-purpose programmable I/O.
AUX1[5:0]
108:113
I/O General-purpose programmable I/O.
AUX1[6]
I/O General-purpose programmable I/O.
114
VFD_DO
O VFD data output.
AUX1[7]
I/O General-purpose programmable I/O.
115
VFD_DI
I
VFD data input.
AUX0[1:0]
118,119
I/O General-purpose programmable I/O.
AUX0[2]
120
I
General-purpose programmable input.
AUX0[3]
121
I/O General-purpose programmable I/O.
AUX0[4]
122
I/O General-purpose programmable input.
VSSV
123,124
G Ground for VDAC circuit.
VDAC
125
O Video DAC V output.
YDAC
126
O Video DAC Y output.
VCCV
127,128
P 2.5V power supply for video DAC circuit.
TYPE
Address Input
Input
Row Address : A0 - A9
Column Address : A0 - A9
Input
Row Address Strobe
Input
Column Address Strobe / Upper Byte Control
Input
Column Address Strobe / Lower Byte Control
Input
Write Enable
Input
Output Enable
Input / Output Data Input / Output
Supply
Power (3.3V)
Ground
Ground
- - -
No Connect
103
102
AUX2[2]/SQCK
AUX2[1]/SQSO
AUX2[0]/VFD_CLK
VCC_P
VSS_P
VSS
RESET#
VCC
DBUS15
DBUS11
DBUS13
DBUS12
DBUS11
DBUS10
DBUS9
DBUS8
DBUS7
DBUS6
DBUS5
DBUS4
DBUS3
DBUS2
DBUS1
DBUS0
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
DOE#/MA9
DWE#
DRAS0#
VCC
64 65
VSS
Descriptions
DESCRIPTION

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