Camera Dsp Schematic Diagram - JVC GR-D30UB Specification

CAMERA DSP SCHEMATIC DIAGRAM

0 1 MAIN(CAMERA DSP)
TO TG
5
CLK18
CLK27
CLK54
ID
PBLK
OBCLP
XAVD
XAHD
IC4202
SHP
MM1613AN-X
SHD
L4201
NQR0129-002X
REG_4.8V
T
C4202
4 0.1
C4203
1
TO CCD
TL4201
CCD_OUT
C4206 C4209
1
R4201
C4210
C4211
TO CPU
CDS_CS
CAM_OUT
CAM_CLK
BUS15
3
ADDT15
BUS14
ADDT14
BUS13
ADDT13
BUS12
ADDT12
BUS11
ADDT11
BUS10
ADDT10
BUS9
ADDT09
BUS8
ADDT08
BUS7
ADDT07
BUS6
ADDT06
BUS5
ADDT05
BUS4
ADDT04
BUS3
ADDT03
BUS2
ADDT02
BUS1
ADDT01
BUS0
ADDT00
CDWE
CDWE
CDDSTB
CALE
CDALE
CAM_CS
CAM_CS
MVD
MFLD
MFLD
OMT
2
OMT
DSP_RST
DSP_RST
TO OP_DRIVER
IRIS_C
IRIS_C
CAM_VD
CAM_VD
IRIS_PWM
IRIS_PWM
CLK4M5
CLK4M5
TO AUDIO
S_SHUT
TO CPU
OSD_VD
TO VIDEO_I/O
CLK27B
CLK27A
1
A
R4345
0Ω
R4344
0Ω
R4346
0Ω
R4342 0Ω
R4343
0Ω
R4205
C4201 0Ω
10 /6.3
C4205 C4204
0.1 0.1
C4207
AVDD D9
C4208
0.1
BLKSH D8
D7
BLKFB
1
IC4201
CDSIN D6
0.1
BLKC HD49340ANP-X D5
33k
BIAS D4
0.1
AVDD D3
AVSS D2
0.1
ADCIN D1
C4301
0.1
C4212
0.1 BUS15
BUS14
C4213 C4216
BUS13
C4214
0.1 0.1
0.1 BUS12
BUS11
R4202 0Ω
BUS10
R4203 0Ω
BUS9
R4204 0Ω
BUS8
BUS7
BUS6
BUS5
BUS4
BUS3
BUS2
BUS1
BUS0
CDWE
R4304 0Ω
CALE
R4306 0Ω
CAM_CS
R4339 0Ω
TL4301
R4354 0Ω R4340
MFLD
IC4303 R4341 0Ω
TL4302
OMT
DSP_RST
CK VCC
R4305
C4318
D PR
Q CLR
GND Q
C4302
0.1
C4317
0.1
IRIS_C
CAM_VD
IRIS_PWM
R4301
CLK4M5
22
NOTE: The parts with marked ( ) is not used.
B C
R4310
0Ω
R4312
R4311
C4312
0.1
CLK18
CLK27
CLK54
ID
OBLK
OBCP
VDTG
HDTG
NC
NC
ADIN9
ADIN8
ADIN7
ADIN6
ADIN5
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
NC
VSS
VDDS
NC IC4301
BUS15
BUS14
BUS13
BUS12
JCY0200
BUS11
BUS10
BUS9
BUS8
BUS7
BUS6
BUS5
BUS4
BUS3
BUS2
BUS1
BUS0
WE
RE
AS
CS
HDCPU
VDCPU
FLDCPU
FRP
OMT
CLR
NC
VDDS
VSS
NC
SDRV
MDRV
VDMDA
PWM
CLK45
NC
R4308
R4326
C4303 47
47
0.1
R4307
47
R4347
R4353
C4316
0Ω
0.01
C4304 C4305
0.1 0.1
R4348
R4355
0Ω
0Ω
R4349 0Ω
R4351 0Ω R4350 R4352
0Ω 0Ω
D
2-15 2-16
R4338 R4337 R4336 R4335
0Ω 0Ω 0Ω 0Ω
C4311 C4310 C4309
0.1 0 .1 0.1
VDDC
VGND
VDDC
NC
AY00
AY01
AY02
AY03
AC00
AC01
AC02
AC03
INHA
0Ω
R4334
INVA
0Ω
R4333
ANACTL
0Ω
R4332
NC
C4308
VDDC
0.1
VGND
VDDC
NC
R4331
OUTV
0Ω
OUTH
0Ω
R4330 DYI0
DYI0
DYI1
DYI1
DYI2
DYI2
DYI3
DYI3
DCI0
DCI0
DCI1
DCI1
DCI2
DCI2
DCI3
DCI3
NC
R4329
INV
0Ω
INH
0Ω
R4328 DYO0
DYO0
DYO1
DYO1
DYO2
DYO2
DYO3
DYO3
DCO0
DCO0
DCO1
DCO1
DCO2
DCO2
DCO3
DCO3
NC
VDDC
VGND
C4307
VDDC
0.1
VDDC
VGND
VDDC
VGND
VDDC
NC
R4320
T
R4318 R4316 R4303
C4306
C4313
0.1 10 /6.3
C4314
0.1
R4309 R4302
0Ω
R4319
0Ω
R4356 R4317
0Ω
0Ω
TL4312 TL4315
TL4313 TL4303
TL4314
R4314 R4327
0Ω
R4315
0Ω
E F
TO DSC
DSYO7
DSYO7
DSYO6
DSYO6
DSYO5
DSYO5
DSYO4
DSYO4
DSYO3
DSYO3
DSYO2
DSYO2
DSYO1
DSYO1
DSYO0
DSYO0
DSCO7
DSCO7
DSCO6
DSCO6
DSCO5
DSCO5
DSCO4
DSCO4
DSCO3
DSCO3
DSCO2
DSCO2
DSCO1
DSCO1
DSCO0
DSCO0
CLKDSC
CLKDSC
HDDSC
HDDSC
VDDSC
VDDSC
FLDDSC
FLDDSC
DSYIO7
DSYIO7
DSYIO6
DSYIO6
DSYIO5
DSYIO5
OUT_Y0 DSYIO4
DSYIO4
OUT_Y1 DSYIO3
DSYIO3
OUT_Y2 DSYIO2
DSYIO2
OUT_Y3 DSYIO1
DSYIO1
DSYIO0
DSYIO0
OUT_C0 DSCIO7
DSCIO7
OUT_C1 DSCIO6
DSCIO6
OUT_C2 DSCIO5
DSCIO5
OUT_C3 DSCIO4
DSCIO4
DSCIO3
DSCIO3
OUT_HS DSCIO2
DSCIO2
OUT_VS DSCIO1
DSCIO1
TBCCTL DSCIO0
DSCIO0
TO AV STRM
OUTV
OUT_HS
OUTH OUT_HS
OUT_VS
OUT_VS
TBCCTL
TBCCTL
OUT_Y3
OUT_Y3
OUT_Y2
OUT_Y2
OUT_Y1
OUT_Y1
OUT_Y0
OUT_Y0
OUT_C3
OUT_C3
OUT_C2
OUT_C2
OUT_C1
OUT_C1
OUT_C0
INV OUT_C0
INH
TO DV_MAIN
OUTV
OUTV
OUTH
OUTH
DYI0
DYI0
DYI1
DYI1
DYI2
DYI2
DYI3
DYI3
DCI0
DCI0
DCI1
DCI1
DCI2
DCI2
IC4302 DCI3
DCI3
R1160N151B-X INV
INV
INH
INH
C4315
DYO0
0.1
DYO0
DYO1
DYO1
DYO2
DYO2
DYO3
DYO3
EC CE DCO0
DCO0
GND DCO1
DCO1
VOUT VDD DCO2
DCO2
DCO3
DCO3
R4321
0Ω
L4301
NQR0129-002X
REG_1.8V
REG_3.1V
L4302
GND
NQR0129-002X
y10335001a_rev0.1
G