JVC GR-D30UB Specification page 29

VIDEO BLOCK DIAGRAM (2/2)
IC3001(DVMAIN)
0 1 MAIN
257
YSO0
VIDEO I/F
YSO3
258 (VBID DET
RAM)
193
BRSO0
BRSO3
194
122
OUTH
5 43
OUTV
116
YSI0
YSI3
117
RAM
(CLOCK
255
BRSI0
CONV)
BRSI3
191
TO
39
CAMERA DSP
INH
a
119
INV
TO
CAMERA DSP
CLK27 38
OSC27I
TO
CAMERA DSP
b
TO CPU
ADDTO0 67
AD0
AD15
ADDT15 150
4 DV_RST 64
XRST
DALE 142
CPUALE
CDWE 212
XCPUDSTB0
CDDSTB 143
XCPUDSTB1
DRWSEL 213
XCPURW
TO
CAMERA DSP
c
DV_WATT 66
CPUWAIT
TO
CPU
d
3
*4
DSC
CN111 CN8001
DSYIO0
TO DSYIO7
CAMERA DSP
DSCIO0
DSCIO7
DSYO0 191
DSYO7
190
DSCO0 237
DSCO7
235
2
CLKDSC
HDDSC
VDDSC
FLDDSC
R8068 C8026
R8022
R8032
CLK27B
TO TG
DSC_WKUP
DSC_CS
DSC_CLK
DSC_DT_OUT
DSC_DT_IN
USBDOWN
DSC_RST
MXDT_OUT
TO
CPU CAPT_REQ
DSC_STS
D8001
TO
3 1
J502
IC8004
1
FLSH_RST
TO
IC8003-12PIN
A
COMPRESS OUTER ECC RAM INNER ECC
(DCT,VLC (ENC/DET) (SUB/AUX) (ENC/DEC)
VLD WORK
RAM)
FORMATTER
(Formatting
Sync Detect
ID Protect
De-formatting)
RAM RAM RAM
(CLOCK (CLOCK (CLOCK
CONV) CONV) CONV)
D-RAM I/F
IEE1394 AUDIO
LINK (WORK
(ISO/ RAM
PROGRAM
ASYNC
FIFO) RISC
CORE)
(DECK_DSP)
R3034
IC8001
246
YIO0
YIO7 CN103
244 MMC_DATA
174
SDI3
2
173 MMC_CLK
188
CIO0 SCK3 5
250 MMC_CMD
SDO3 7
CIO7
247 117 M32_MMC
GIO20 9
39 16
YIN0 ARM_D15
DSC R/D_DATA
YIN7 ARM_D0
108
7 20
CIN0
ARM_A19
DSC R/D_ADRESS
CIN7
ARM_A0
20
176
CLKIN1
9 29 45
25
172
HDIN
A0~A19 DQ0~DQ15
249
VDIN
IC8003
212
FID
(16M_FLASH
199
MXI RAM)
219 26
11
CLKIN2
EM_CS_O FLSH_CE
239
85 28
FLSH_OE
EM_OE
9
11
FLSH_WE
EM_WE
157 12
GIO0 RESET
125
GIO18
206
FROM
SCLK1
205
IC1001-6PIN
SDI1
184 X8002
SDO1
49 2
135 M48XI
GIO13
30 3 CXO
182
M48XO
RESET
127
48MHz
GIO16
146
GIO7
138
GIO11
16 2
DQ0
SDR_DQ0
204 SDRAM_DATA
USB_DN SDR_DQ31 DQ31
122 56
129 25
SDR_A0
A0
SDRAM_ADRESS
SDR_A10 A10
151 24
IC8002
159 67
221
SDR_CKE CKE
USB_DP
51 68
64M
SDR_CLK CLK
20 SDRAM
177
SDR_CS CS
18
201
CAS
SDR_CAS
160 71
DQM1
SDR_DQMLH
200 19
RAS
SDR_RAS
17
193
SDR_WE WE
16
180
SDR_DQMLL DQMO
B C
182 FSPLLCTL
PWMAUDIO
173 RECCTL
RECCTL
100 RECDATA
RECDATA
174 RECCLK
RECCLK
242 SPA
SPA
240
HID1 TO
HSP
98
CPU
HID
243 TSR
TRKREF
101 FRP
FRREF
168
AGC_OUT
ADVIN0
IC3002
(DVMAIN)
IC3005
11 1
AMP+
DAAOUT0
4
237
2 AMPO
4 FSPLLCTL
DAAOUT1
AMP- AO5
18 RECCADJ
AO1
19 ATF_GAIN
AO2
106 5
AO6
DISCRI
R3009 R3010
23 M_VCOCTL
PWM27O
R3011
C3024
104
OSC27O
L3007
105 D3001
OSC27I
C3023
24
CLK27BO
TO
SD/MMC
SOCKET
D
2-55 2-56
0 5 PREMDA
IC3501
CN110 CN401
HID3 HID3 38
38 3 HID3
TO PBH PBH 41
36 5 PB_H
CPU
RECH RECH 42
35 6 REC_H
HID1 HID1 40
37 4 HID1
REC_CLK REC_CLK 9
2 4
16 25 REC_CLK
REC_DATA IC3502 REC_DATA 7
18 23 REC_DATA
REC_CTL REC_CTL 44
34 7 R_CTL
MONI_CHG MONI_CHG 12
8 33 MONI_CHG
(PRE/REC)
TO
JIG CONN
(CN105)
ENV_OUT ENV_OUT 48
PB_MONI
33 8
ATF_GAIN ATF_GAIN 60
27 14
GC_OUT GC_OUT 57
30 11 AGC_BUFF_OUT
RECCADJ RECCADJ 10
19 22 REC_GAIN
*1 WITH ANALOG INPUT MODEL
*2 WITHOUT ANALOG INPUT MODEL
*3 WITH EDIT MODEL
*4 WITH DSC MODEL
E F
24
Y2
CN402
HEAD
6 2F
25
X2 7 2S
3 1S
20
X1 2 1F
19
Y1
AIMCK
AILRCK
TO IC3001 AIBCK TO
AIDAT AUDIO
AODAT
TPA+
TPA-
TPB+
DV IN/OUT
TPB-
DV
J501
PD_L
AU_CLK
AU_DATA
AUDIO_CS TO
AUDIO
S_SHUT
G