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4.10
DSP SCHEMATIC DIAGRAM
0 1 MAIN (DSP)
TO TG
PBLK
TL4405
AD_CLK
CLK27
CLK18
CLK13
ID
XAVD
XAHD
VGAT
5
OBCLP
SHD
SHP
TL4201
C4205
C4204
0.1
0.1
TO CCD
CN5001
CN107
CCD_OUT
AVSS
NC
R4203
0Ω
AVSS
D9
C4208
0.1
AVDD
TIMING
D8
C4209
1
BLKSH
GEN
D7
BLKFB
D6
CDS
10bit
4
TL4202
C4206
1
CDSIN
D5
ADC
C4210
BLKC
D4
0.1
R4205
33K
BIAS
D3
C4211
0.1
AVDD
PGA
I/F
D2
NC
D1
AVSS
D0
ADCIN
NC
C4212
0.1
C4201
C4213
100
0.1
C4217
[CDS/AGC/AD]
C4215
0.1
0.1
IC4201
C4214
0.1
HD49334F
C4203
CDS_CS
CLK_OUT
IC4202
DATA_OUT
[3V_REG.]
CRWSEL
MM1385HN-X
CDSTB
CALE
BUS15
C4202
BUS14
3
0.1
BUS13
BUS12
BUS11
BUS10
BUS9
BUS8
BUS7
BUS6
TO
BUS5
SYSCON
BUS4
BUS3
BUS2
BUS1
BUS0
DSP_RST
MVD
OMT
MFLD
VC0
VC1
VC2
BLKA
BLKC
VC3
BLKB
2
DOT_CLK
OSD_VD
OSD_HD
TO D.CPU,
OP.DRV
CAM_VD
CLK4M5
TO OP.DRV
IRIS_PWM
TO DVMAIN
TDO
TL4350
TDB
TL4351
TRST
TL4352
1
TMS
TL4353
TCMK
TL4354
∗
NOTE : The parts with marked ( ) is not used.
A
B
TL4301
C4342
C4341
0.1
0.1
C4343
VDDI
0.1
VSS
MEMORY_IN
MEMORY_OUT
C4344
ADDVDDE
0.1
CLK27
CLK18
CLK
CLK13
ID
EIS
GEN
VDTG
HDTG
FMC
LHFO
&SSG
C4345
ADDVDDE
0.1
VSS
ADIN9
ADIN8
ADIN7
ADIN6
KIZU
ADIN5
ADIN4
ADIN3
ADIN2
ADIN1
ADIN0
C4346
VDDI
0.1
ADDVSS
C4347
ADDVDDE
0.1
PBLK
R4339
0Ω
RE/RW
WE/DSTB
R4340
0Ω
ALE/ASTB
/4
BUS15
BUS14
IWD
BUS13
BUS12
BUS11
1
BUS10
BUS9
BUS8
BUS7
BUS6
BUS5
CPU
BUS4
BUS3
I/F
BUS2
BUS1
BUS0
TL4304
VSS
CLR
VDCPU
TL4306
HDCPU
TL4305
FRP
TL4307
OMT
CONTROL
AFBEND
TL4308
TL4309
FLDCPU
BEND
TL4310
TL4311
VSS
GT_X
TL4312
VPD
CS
OSD
TL4313
GT_S
C4348
VDDI
I/F
0.1
ANA
CLKOSD
IC4301
HDOSD
I/F
VDOSD
JCY0158
BLK1
R4341
BLK2
0Ω
[CAMERA_DSP]
VC1
VC2
VR
VG
VB
ANALOG_IN
VBLK
ADDVSS
C4301
0.1
#Difference Point
R4302
R4303
∗
NTSC
0Ω
∗
PAL
0Ω
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
C4340
C4338
C4337
0.1
0.1
0.1
DVC_IN
DVC_OUT
ADDVDDE
DVC
I/F
ADDVDDE
ADDVSS
ADDVDDE
CVF
ADDVDDE
ADDVSS
ADDVDDE
EOUT12
EOUT11
EOUT10
ENC
SELECT
SENC
EVR
AVDDE1
DAC
VREFH1
VREFL1
Y/C
AVSSE1
HNR
AVDDE2
VREFH2
VREFL2
AVSSE2
AVDDE3
VREFH3
VREFL3
AUTO
AVSSE3
Y
DAC
AVDDV1
AVSSV1
C
Y2_OUT
DAC
GY
DAC
RY
R-Y_OUT
DAC
B-Y_OUT
BY
VREFVF
DSC
DAC
VREFLK
I/F
K
VREFHK
KASHA
AVSSV2
DAC
AVDDV2
DACTEST
DSC_OUT
DSC_IN
ADDVSS
C4303
C4304
0.1
0.1
NQR0129-002X
C4305
10
/6.3
T
D
E
4-21
4-22
[FILED_MEMORY]
[FILED_MEMORY]
VDDI
VSS
C4335
0.1
GT_B
TL4303
GT_A
R4337
TL4302
HRP2
0Ω
HRP1
NRZ0034-101W
HDCVF
RA4301
100
VDCVF
VSS
VDDE
VSS
VDDE
VSS
NQR0129-002X
TL4317
EOUT9
TL4316
EOUT8
EOUT7
EOUT6
EOUT5
EOUT4
EOUT3
EOUT2
EOUT1
C4329
0.1
NC
C4328
R4336
0.1
0Ω
R4334
∗
C4327
DVDDM
0.1
R4335
∗
C4324
10
/6.3
R4333
L4307
0Ω
10µ
C4323
T
0.1
C4326
∗
C4325
0.1
NC
Y_OUT
C4321
0.1
VREFY
R4313
R4344
IREFY
2.7k
0Ω
C4320
C_OUT
0.1
VREFC
R4312
R4343
IREFC
2.7k
0Ω
C4319
0.1
R4314
R4311
12k
IREFVF
12k
R4315
K_OUT
10k
C4318
0.1
R4342
∗
C4350
0.1
AVSSA
DVDDM
AVDDA
VSS
∗
VDDI
T
C4317
C4316
∗
0.1
R4345
∗
TL4314
L4304
22µ
T
C4313
C4312
22
/6.3
0.1
L4306
NQR0129-002X
L4301
C4310
C4309
10
/6.3
0.1
VOUT
C4306
NOISE
0.1
C4308
0.1
GND
C4307
T
VIN
10
/6.3
CONT
C4311
1
IC4304
L4302
NQR0129-002X
∗
[2.5V_REG.]
F
TO
MAIN IF CN101
HRP
HDCVF
VDCVF
OUTH
OUTV
DYI3
DYI2
DYI1
DYI0
TO DVMAIN
DCI3
DCI2
DCI1
DCI0
INH
TO SYSCON, DVMAIN
INV
DYO3
DYO2
DYO1
DYO0
TO DVMAIN
DCO3
DCO2
DCO1
DCO0
TO OP.DRV
H_OFFSET
H_GAIN
C4331
10
/6.3
L4305
DUMP_CTL
TO PRE/REC
NOSIG_LV
FSPLLCTL
TO DVMAIN
M_VCOCTL
ATF_GAIN
TO PRE/REC
PBVCOCTL
TO DVMAIN
TO PRE/REC
RECCADJ
TO DVMAIN
PBPLLCTL
TO AUDIO
S_SHUT
TO V OUT
DV_Y
DV_C
REG_2.5V
(NC)
R4346
0Ω
TO MONI IF
DA_B
DA_R
DA_G
TO REG
REG_1.8V
REG_3V
GND
L4201
REG_4.8V
NQR0129-002X
y10273001a_rev0
G
H
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