Sony SCD-XB780 Service Manual page 58

SCD-XB780
• MAIN BOARD IC901 CXP973064-221R (CPU)
Pin No. Pin Name
1
MUT LOAD
2 AMUTE
3 DOCTRL
4
MUT 2D
5 MODE DAC
6
SP ON
7 FCS JMP1
8 FCS JMP2
9 SENS CD
10 —
11 XCS IO
12 XCS DVD
13 VSS
14 to 21 D0 to D7
22 INT0 DVD
23 INT1 DVD
24 T SENS
25 MIRR RF
26 SCOR CD
27 RDY DSD
28 A1IN
29 COUT CD
30 IN SW
31 OUT SW
32 —
33 SQSO CD
34 DATA CD
35 CLOK CD
36 XLAT CD
37 SQCK CD
38 XRST
39 VSS
40 XTAL
41 EXTAL
42 VDD
43 SPDA
44 APDO
45
LOAD IN
46
LOAD OUT
47 XLAT DSD
48 SIN DSD
49 SOUT DSD
50 SCK DSD
51 MUTE DSD
52 XDIS IO
58
I/O
O
Muting on/off control signal output to the loading motor drive "H": muting on
O
Analog muting control signal output terminal Not used
Digital out on/off control signal output to the digital signal processor
O
"L": digital out off, "H": digital out on
O
Muting on/off control signal output to the focus/tracking coil drive "H": muting on
I Not used
O
Muting on/off control signal output to the spindle motor drive "H": muting on
O
Focus jump 1 signal output
O
Focus jump 2 signal output
I Internal status (SENSE) signal input from the digital signal processor
O
Not used
O
Chip select signal output to the programmable logic device
O
Chip select signal output to the SACD decoder
— Ground terminal (digital system)
I/O
Two-way data bus with the SACD decoder and programmable logic device
I
Interrupt signal input from the SACD decoder
I
Interrupt signal input from the SACD decoder
I Input terminal of disc tray status detection signal from table sensor
I
Mirror signal input from the digital signal processor
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
I
Ready signal input from the DSD decoder "L": ready
I Input terminal of sircs remote control signal from CONTROL A1 II Not used
I
Numbers of track counted signal input from the digital signal processor
I
Loading in switch input terminal "L": loading in
I
Loading out switch input terminal "L": loading out
O Not used
I
Subcode Q data input from the digital signal processor
O
Serial data output to the digital signal processor
O
Serial data transfer clock signal output to the digital signal processor
O Serial data latch pulse signal output to the digital signal processor
O
Subcode Q data reading clock signal output to the digital signal processor
System reset signal input "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
—
Ground terminal (digital system)
I System clock input terminal (20 MHz)
O
System clock output terminal (20 MHz)
—
Power supply terminal (+3.3V) (digital system)
O
Spindle motor control signal output
O Output terminal for offset adjustment of APEO (<z/. pin of SACD decoder)
O
Loading motor drive signal (loading in direction) output
O
Loading motor drive signal (loading out direction) output
O
Serial data latch pulse signal output to the DSD decoder
I Serial data input from the DSD decoder
O
Serial data output to the DSD decoder and digital filter
O
Serial data transfer clock signal output to the DSD decoder and digital filter
O
Muting on/off control signal output to the DSD decoder "H": muting on
O Reset signal output to the programmable logic device "L": reset
Description
Not used