LG GCC-4241N Service Manual page 36

•Pin Assignment
V 1
DD
DQ 0 2
DQ 1 3
V 4
S SQ
DQ 2 5
DQ 3 6
V 7
DDQ
DQ 4 8
DQ 5 9
V 1 0
S SQ
DQ 6 1 1
DQ 7 1 2
V 1 3
DDQ
LD Q M 1 4
WE# 1 5
CA S# 1 6
RA S# 1 7
CS # 1 8
A 1 1 1 9
A 1 0 2 0
A 0 2 1
A 1 2 2
A 2 2 3
A 3 2 4
V 2 5
DD
•Pin Description
Symbol Type
CLK Input
CKE Input
A11 Input
38
5 0
Vss
4 9
D Q 1 5
4 8
D Q 1 4
4 7
V
S SQ
4 6
D Q 1 3
4 5
D Q 1 2
4 4
V
DDQ
4 3
D Q 1 1
4 2
D Q 1 0
4 1
V
S SQ
4 0
DQ 9
3 9
DQ 8
3 8
V
DDQ
3 7
NC
3 6
UD QM
3 5
CL K
3 4
CKE
3 3
NC
3 2
A 9
3 1
A 8
3 0
A 7
2 9
A 6
2 8
A 5
2 7
A 4
2 6
Vss
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When both banks are in the idle state, deactivating the
clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
1 2 3
A
V S S D Q 1 5
B
D Q 1 4 V S S Q
C
D Q 1 3 V D D Q
D
D Q 1 2 D Q 1 1
E
D Q 1 0 V S S Q
F
D Q 9 V D D Q
G
D Q 8
N C
H
N C
N C
J
N C U D Q M
K
N C C L K
L
N C
C K E
M
A 9
A 1 1
N
A 8
A 7
P
A 5
A 6
R
V S S A 4
4 5 6 7
D Q 0
V D D
D Q 1
V D D Q
V S S Q D Q 2
D Q 4 D Q 3
V D D Q D Q 5
V S S Q D Q 6
D Q 7
N C
N C N C
L D Q M
W E #
R A S #
C A S #
N C
C S #
N C N C
A 0 A 1 0
A 2 A 1
A 3 V D D