6.4.2.2
6.4.2.2
6.4.2.2
6.4.2.2
Multiword DMA Transfer Mode
Multiword DMA Transfer Mode
Multiword DMA Transfer Mode
Multiword DMA Transfer Mode
The multiword DMA host interface timing shown in Table 6-6 is in reference to
signals at 0.8 volts and 2.0 volts. All times are in nanoseconds, unless otherwise
noted. Figure 6-2 provides a timing diagram.
Table 6-6
Table 6-6
Table 6-6
Table 6-6
SYMBOL
SYMBOL
SYMBOL
SYMBOL
t0
t0 t0
t0
tD
DIOR–/DIOW– Pulsewidth
tE
DIOR– to Data Valid
tF
DIOR– Data Hold
tFz
DIOR– Data Tristate
tG
DIOW– Data Setup
tH
DIOW– Data Hold
tI
DMACK to DIOR–/DIOW– Setup
tJ
DIOR–/DIOW– to DMACK– Hold
tK
DIOR–/DIOW– Negated Pulsewidth min
tL
DIOR–/DIOW– to DMARQ Delay
tz
DMACK– Data Tristate
1. ATA Mode 2 timing is listed for reference only.
2. The Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT drive tristates
after each word transferred.
3. Symbol tz only applies on the last tristate at the end of a multiword DMA transfer
cycle.
Figure 6-2
Figure 6-2
Figure 6-2
Figure 6-2
Multiword DMA Host Interface Timing
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Cycle Time
Cycle Time
Cycle Time
Cycle Time
2
3
Multiword DMA Bus Interface Timing
Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT
ATA Bus Interface and ATA Commands
1 1 1 1
MODE 2
MODE 2
MODE 2
MODE 2
MIN/MAX
MIN/MAX
MIN/MAX
MIN/MAX
(local bus)
(local bus)
(local bus)
(local bus)
120
min
min
min
min
min
70
max
–
min
5
max
20
min
20
min
10
min
0
min
5
25
max
35
max
25
Quantum
Quantum
Quantum
Quantum
Fireball Plus
Fireball Plus
Fireball Plus
Fireball Plus
AS
AS
AS
AS
AT
AT
AT
AT
120
70
–
5
20
20
10
0
5
25
35
25
6-11