Quantum FIREBALL PLUS AS 10.2 Product Manual page 64

ATA Bus Interface and ATA Commands
Note: Note: Some host systems do not read the Status Register after the Note: Note:
6.4.1.1 6.4.1.1 6.4.1.1 6.4.1.1 Electrical Characteristics Electrical Characteristics Electrical Characteristics Electrical Characteristics
All signals are transistor-transistor logic (TTL) compatible—with logic 1 greater
than 2.0 volts and less than 5.25 volts; and logic 0 greater than 0.0 volts and less
than 0.8 volts.
6.4.1.2 6.4.1.2 Drive Signals Drive Signals
6.4.1.2 6.4.1.2 Drive Signals Drive Signals
The drive connector (J1, section C) connects the drive to an adapter board or
onboard ATA adapter in the host computer. J1, section C is a 40-pin shrouded
connector with two rows of 20 pins on 100-mil centers. J1 has been keyed by
removing pin 20. The connecting cable is a 40-conductor (80-conductor for UDMA
modes 3 and 4 operation) flat ribbon cable with a maximum length of 18 inches.
Table 6-1 describes the signals on the drive connector (J1, section C). The drive
does not use all of the signals provided by the ATA bus. Table 6-4 shows the
relationship between the drive connector (J1, section C) and the ATA bus.
Note: Note: Note: In Table 6-1 the following conventions apply: Note:
Table 6-1 Table 6-1
Table 6-1 Table 6-1
SIGNAL SIGNAL SIGNAL SIGNAL
Reset RESET–
Ground Ground
Data Bus
6-2 Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT
drive issues an interrupt. In such cases, the interrupt may not
be acknowledged. To overcome this problem, you may have to
configure a jumper on the motherboard or adapter board to
allow interrupts to be controlled by the drive's interrupt logic.
Read your motherboard or adapter board manual carefully to
find out how to do this.
A minus sign follows the name of any signal that is asserted as
active low.
Direction (DIR) is in reference to the drive.
IN indicates input to the drive.
OUT indicates output from the drive.
I/O indicates that the signal is bidirectional.
Drive Connector Pin Assignments (J1, Section C)
NAME NAME NAME NAME DIR DIR DIR DIR PIN PIN PIN PIN
IN 1
— 2
I/O 3–18 An 8/16-bit, bidirectional data bus between the
DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION
Drive reset signal from the host system, inverted
on the adapter board or motherboard.
This signal from the host system will be asserted
beginning with the application of power, and held
asserted until at least 25 µs after voltage levels
have stabilized within tolerance during power on.
It will be negated thereafter unless some event
requires that the device(s) be reset following
power on.
ATA devices will not recognize a signal assertion
shorter than 20 ns as a valid reset signal. Devices
may respond to any signal assertion greater than
20 ns, and will recognize a signal equal to or
greater than 25 µs.
The drive has a 10kW pull-up resistor on this signal.
Ground between the host system and the drive.
host and the drive. D0–D7 are used for 8-bit
transfers, such as registers and ECC bytes.