Table 5. Video Input Timing; Table 6. Setup And Hold Timing - Planar EL640.480-AG1 Series User Manual

Table 5. Video Input Timing.

Symbol Name
T1 Frame time
Frame frequency
T2 CP1 High time
T3 CP1 Period
S (FRAME)
CP1 (LINE)
tCLK
tCL tCH
CP2 (SHIFT)
UD0 to UD3
LD0 to LD3
Figure 2. Setup and Hold Timing Diagram.

Table 6. Setup and Hold Timing.

Symbol Name
tS21 CP1 allowance from CP2
tS12 CP2 allowance from CP1
tS3 CP1 allowance to CP2
tSU Setup time
tHOLD Hold time
tR Rise time
tF Fall time
tCLK CP2 clock cycle
tCL CP2 clock low time
tCH CP2 clock high time
If CP1 (HS) low time >160 CP2 pulses, then non-displayed pixels should be at
a logic low.
EL640.480 AG1 Series User's Manual (020-0350-00B)
AG1
Min Max
8.3 ---
--- 120
60 ---
34.5 ---
tR
tS21
tR tF
tSU tHOLD
Min.
0
200
50
50
40
154
60
60
AG1 ET
Min Max Units
8.3 --- ms
--- 120 Hz
60 --- ns
31.5 --- µs
tSU tHOLD
tF
tS12
tS3
Max Unit
ns
ns
ns
ns
ns
30 ns
30 ns
ns
ns
ns
10