Video Input Timing; Setup And Hold Timing; Figure 4. Setup And Hold Timing; Table 5. Video Input Timing - Planar EL512.256-H Series User Manual

Video Input Timing

Setup and Hold Timing

EL512.256-H Series Operations Manual (020-0354-00A)
9
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Table 5. Video Input Timing.

Description
1
T1 Vertical Front Porch
2
T2 VS HIGH/LOW time
T3 Vertical Period
VS frequency
Description
T4 HS setup to VS
T5 HS hold from VS
3
T6 HS Low Time
4
T7 HS High Time
T8 HS period (tHS)
Notes:
1 This time is needed to display the last row and to change the frame.
2
Only rising edge is used.
3
Video Clock VCLK should be kept running.
4
The values for two bit parallel mode are 256/256 tVCLK. The number
of VCLK pulses during HS high time should be even.

Figure 4. Setup and Hold Timing.

Table 6. Setup and Hold Timing.

Symbol Description
tVCLK VCLK period
VCLK frequency
Min typ
100
1
256 tHS + T1
70
Min Typ
1
3
4
512 512
50
Min
33ns
Max Unit
µs
tVCLK
75 Hz
Unit
tVCLK
µs
tVCLK
tVCLK
µs
Max
30 MHz