Intel D875PBZ Specification Update page 25

Table 3. Specifications (continued)
Reference Specification
Name Title
ATX/ATX12V Power
ATX12V
Supply Design
Guide
BIS Boot Integrity
Services (BIS)
Application
Programming
Interface (API)
Double Data Rate
DDR
SDRAM (DDR) SDRAM
Specification
Design Specification
for a 184 Pin DDR
Unbuffered DIMM
®
Intel JEDEC DDR
200/266 Unbuffered
DIMM Specification
Addendum
Enhanced Host
EHCI
Controller Interface
Specification for
Universal Serial Bus
EPP IEEE Std 1284.1-
1997
(Enhanced Parallel
Port)
Bootable CD-ROM
El Torito
Format Specification
Low Pin Count
LPC
Interface
Specification
®
Intel Desktop Board D875PBZ Specification Update
Version, Revision Date
and Ownership
Version 1.2,
August 2000,
Intel Corporation.
Version 1.0,
August 4, 1999,
Intel Corporation.
Version 2.0,
May 2002,
JEDEC Solid State
Technology Association.
Revision 1.0,
October 2001,
JEDEC Solid State
Technology Association.
Revision 0.9,
September 27, 2001,
Intel Corporation.
Revision 1.0,
March 12, 2002,
Intel Corporation.
Version 1.7, 1997,
Institute of Electrical and
Electronic Engineers.
Version 1.0,
January 25, 1995,
Phoenix Technologies
Limited and International
Business Machines
Corporation.
Revision 1.0,
September 29, 1997,
Intel Corporation.
The information is
available from...
http://www.formfactors.org
/developer/specs/atx/atxs
pecs.htm
http://www.intel.com/labs/
manage/wfm/wfmspecs.ht
m
http://www.jedec.org/
http://www.jedec.org/
http://developer.intel.com/
technology/memory/index.
htm
http://developer.intel.com/
technology/usb/download/
ehci-r10.pdf
http://standards.ieee.org/r
eading/ieee/std_public/de
scription/busarch/1284.1-
1997_desc.html
http://www.phoenix.com/re
sources/specs-cdrom.pdf
http://www.intel.com/desig
n/chipsets/industry/lpc.ht
m
continued
19