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QuickSpecs
Standard Features
Security
Availability
Power-on password
Administrator's password
HP iLO 4 On System Management Chipset with:
SSL encryption
Secure Shell version 2
Advanced Encryption Standard (AES) and Triple Data Encryption Standard (3DES) on browser,
CLP and XML scripting interface
AES and RC4 encryption of video
External USB port enable/disable
Network server mode
Serial interface control
TPM (Trusted Platform Module) 1.2 option
Advanced Encryption Standard (AES)
Intel® Advanced Encryption Standard-New Instructions (AES-NI)
Memory
Advanced ECC uses single device data correction (SDDC) to detect and correct single and all multi-bit
error that occurs within a single DRAM chip. Both x4 and x8 SDDC are supported (x8 requires
lockstep mode).
Memory online spare mode (also known as rank spare mode) detects a rank that is degrading and
switches operation to the spare rank.
Memory Lockstep mode is used to correct a single x8 DRAM device failure on a DIMM. The DIMMs in
each paired memory channel must have identical HP part numbers.
Memory demand and patrol scrubbing to prevent accumulation of correctable errors and reducing
the likelihood of unplanned downtime.
Failed DIMM isolation improves the service time thus improving the overall system availability.
Address parity protection available on RDIMMs and LRDIMMs detects address bit errors to improve
service time and overall system availability.
Storage
Two (2) Small Form Factor hot-plug SAS/SATA/SSD drive bays.
Integrated HP Smart Array P220i Controller with 512MB FBWC, RAID 0 and 1 support, and
upgradeable firmware with recovery ROM capability.
Optional HP D2200sb Storage Blade for direct attachment of up to 12 drives to an adjacent blade
within the c-Class enclosure. (Available with single-width WS460c only)
Optional dual-port Fibre Channel mezzanine card for redundant SAN connections. (With
configurations where mezzanine slot is available)
Processor/Chipset
Processor internal sensors & thermal control protection against over-temperature conditions.
Cache parity/ECC protects cache data from accidental data corruption.
Machine Check Architecture (MCA) detects and captures hardware errors such as system bus,
memory ECC, parity, and cache, and improves service time.
Intel® QPI Protocol Protection allows detection of data errors using a checksum of 8-bits.
Core Disable for FRB (fault resilient boot) allows a system to power-on despite a failing core-pair. It
uses BIST (built-in self test) results to detect a failure and disables the target core-pair upon
subsequent boot.
DA - 14409 North America — Version 16 — December 13, 2013
HP ProLiant WS460c Gen8 Workstation Blade
Page 13
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