Dram Timing Configuration - Foxconn A79A-S User Manual

When select [Manual], the following two items will appear.
► DcqBypassMax
The DRAM controller arbiter normally allows transactions to pass other transactions in order to
optimize DRAM bandwidth. This field specifies the maximum number of times that the oldest
memory-access request in the DRAM controller queue may be bypassed before the arbiter
decision is overridden and the oldest memory-access request is serviced instead.
► FourActWindow
This item specifies the rolling tFAW window during which no more than 4 banks in a 8-bank
device are activated, per JEDEC DDR2 specification. For example, if this item is set to 10
clocks and an activate command is issued in clock N, then no more than three further activate
commands may be issued in clocks N+1 through N+9. To program this field, BIOS must con-
vert the tFAW parameter into MEMCLK cycles by dividing the highest tFAW (in ns) across all
DIMMs connected to the channel by the lowest period (highest frequency) of MEMCLK (in ns)
over all P-states and rounding up to the next integer.

DRAM Timing Configuration

► Memory Speed Mode
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