Kenwood TK-7102 Service Manual page 11

Wide/Narrow Changeover Circuit
The Wide port (pin 92) and Narrow port (pin 91) of the
CPU is used to switch between ceramic filters. When the
Wide port is high, the ceramic filter SW diodes (D13, D15)
cause CF1 to turn on to receive a Wide signal.
When the Narrow port is high, the ceramic filter SW diodes
(D13, D15) cause CF2 to turn on to receive a Narrow signal.
IF_IN
CF1
(Wide)
CF2
(Narrow)
D13
Narrow
IC6 91pin
Fig. 3 Wide/Narrow changeover circuit
AF Signal System
The detection signal from IF IC (IC5) goes to AF amp (IC3)
to adjust the gain and is output to AF filter (IC10) for charac-
terizing the signal. The AF signal output from IC10 and the
DTMF signal, BEEP signal are summed and the resulting sig-
nal goes to the D/A converter (IC3). The AFO output level is
adjusted by the D/A converter. The signal output from the
D/A converter is input to the audio power amplifier (IC16).
The AF signal from IC16 switches between the internal
speaker and speaker jack (J1) output.
IC5 IC3 IC10
DEO
AF AF
IF IC
AMP Filter
FIg. 4 AF signal system
CIRCUIT DESCRIPTION
IC5
IF System
MIX_O
R73
Wide
IC6 92pin
R77
D15
IC3 IC102 SP
D/A
AF PA
CONV.
Squelch Circuit
The detection output from the FM IF IC (IC5) passes
through a noise amplifier (Q18) to detect noise. A voltage is
applied to the CPU (IC6). The CPU controls squelch accord-
ing to the voltage (SQIN) level. The signal from the RSSI pin
of IC5 is monitored. The electric field strength of the re-
ceive signal can be known before the SQIN voltage is input
to the CPU, and the scan stop speed is improved.
IC5 NOISE AMP
AF
IF
SYSTEM
RSSI
Fig. 5 Squelch circuit
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal
for reception and the RF signal for transmission.
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC1 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output sig-
nal is buffer amplified by Q15, then divided in IC1 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC1. The output signal from the phase
comparator is filtered through a low-pass filter and passed
to the VCO to control the oscillator frequency. (See Fig. 6)
VCO
The operating frequency is generated by Q11 in transmit
mode and Q10 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D10 and
D12 in transmit mode and D9 and D11 in receive mode).
The TX/RX pin is set low in receive mode causing Q12 and
Q7 to turn Q11 off, and turn Q10 on. The TX/RX pin is set
high in transmit mode. The outputs from Q10 and Q11 are
amplified by Q15 and sent to the buffer amplifiers.
TK-7102
Q18
D18 IC6
SQIN
DET
CPU
RSSI
11