Table 86.Read Dma Command (C8H/C9H); Read Dma Queued (C7H) - Hitachi T7K250 - Deskstar - Hard Drive Specifications

12.16 Read DMA Queued (C7h)

Table 87: Read DMA command (C8h/C9h)
Command Block Output Registers
Register
Data
Feature
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
Error Register
7 6 5
CRC UNC 0
V V 0
This command executes in a similar manner to a READ DMA command. The device may perform a bus release or
it may execute the data transfer without performing a bus release if the data is ready to transfer.
If the device performs a bus release, the host shall reselect the device using the SERVICE command.
When the data transfer is begun, the device does not perform a bus release until the entire data transfer has been
completed.
Output parameters to the device
Feature
Sector Count
Sector Number
Cylinder High/Low
H
Input parameters from the device on bus release
Sector Count
Sector Number, Cylinder High/low, H n/a.
SRV
7 6 5 4 3 2 1 0
- - - - - - - -
- - - - - - - -
V V V V V V V V
V V V V V V V V
V V V V V V V V
V V V V V V V V
1 L 1 D H H H H
1 1 0 0 0 1 1 1
4 3 2 1
IDN 0 ABT T0N AMN
V 0 V 0
The number of sectors to be transferred. A value of 00h indicates that 256 sectors are to be
transferred.
Bits 7 - 3 (Tag) contain the Tag for the command being delivered.
Starting sector number or LBA address bits 7 - 0.
Starting cylinder number or LBA address bits 23 - 8.
Starting head number or LBA address bits 27 - 24
Bits 7 - 3 (Tag) contain the Tag of the command being bus released.
Bit 2 (REL) is set to one.
Bit 1 (I/O) is cleared to zero.
Bit 0 (C/D) is cleared to zero.
Cleared to zero when the device performs a bus release. This bit is set to one when the
device is ready to transfer data.
Deskstar T7K250 Hard Disk Drive Specification
Command Block Input Registers
Register
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Status
0 7 6 5
BSY RDY DF DSC DRQ
V 0 V 0
145
7 6 5 4 3 2 1 0
- - - - - - - -
see below
V V V V V V V V
V V V V V V V V
V V V V V V V V
V V V V V V V V
- - - - H H H H
see below
Status Register
4 3 2 1
COR IDX
V - 0 -
0
ERR
V