Device/Head Register; Status Register; Command Register - Hitachi DK23CA-10 - 10 GB Hard Drive Specifications

6.3.1.8 Device/Head Register

This register has the binary coded address of device and head selected. The head numbers begins
with "0".
Bit
Name
a) Bits HS3 to HS0 are head addresses to be selected. HS3 is the highest bit. The address of the
currently selected head is displayed in this register when a command is completed. In case of
LBA mode, these bits HS3 to HS0 are applied to LBA bits 27 to 24.
b) DRV is a device selection bit. 0=DRV0, 1=DRV1
c) L is the sector address mode select. 0=CHS mode, 1=LBA mode

6.3.1.9 Status Register

The current device status is reflected in this register. The contents are updated at the completion of each
command. If BSY=1, no other bits in this register are valid. When BSY is cleared, the other bits in this
register shall be valid within 400 ns. If the host reads this register when an interrupt is pending, it is
considered to be the interrupt acknowledge, and the pending interrupt is then cleared.
Bit
Name
a) ERR (Error): This bit indicates that an error occurs during the execution of a command. For more
information, refer to the description of the Error register.
b) IDX(Index): This bit is set once per disk revolution.
c) CORR(Corrected Data): This bit indicates that a correctable error has occurred and data has been
corrected. The data transfer is not interrupted.
d) DRQ(Data Request): This bit indicates that the device is ready to transfer data between the host and
the device.
e) DSC(Device Seek Complete): This bit indicates that the device head is located on the specified track.
If an error has occurred, the value of this bit is not changed until the host reads the Status register.
f) DFW(Device Write Fault): This bit indicates that an error has occurred during a Write operation. If an
error has occurred, the value of this bit is not changed until the host reads the Status register.
g) DRDY(Device Ready): This bit indicates that the device is ready to respond any command. If an error
has occurred, the value of this bit is not changed until the host reads the Status register. This bit is
cleared when the power is turned on and then kept cleared until the device gets ready to accept any
command.
h) BSY(Busy): This bit is specified when the device accesses the Command Block Registers. When BSY
is 1,the host cannot access the Command Block Registers. If the Command Block Registers are read
when BSY is 1, all contents of the Status Register are returned.

6.3.1.10 Command Register

The command code is sent to this register. After it is written, execution begins.
K6602637
Rev.3
02.27.01
7 6 5
- L -
7 6 5
BSY DRDY DWF
4 3 2
DRV HS3 HS2
4 3 2
DSC DRQ CORR
- 33 -
1 0
HS1 HS0
1 0
IDX ERR