Low Pin Count (Lpc) Interface; Serial Peripheral Interface (Spi); Compatibility Module; Advanced Programmable Interrupt Controller (Apic) - Dell R210 II Technical Manual

8.7 Low-Pin Count (LPC) Interface
The LPC bridge function of the PCH resides in PCI Device 31: Function 0. In addition to the LPC bridge
function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power
Management, System Management, GPIO, and RTC.

8.8 Serial Peripheral Interface (SPI)

The chipset implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI
flash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet,
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Intel Active Management Technology, and integrated Intel Quiet System Technology. The chipset
supports up to two SPI flash devices with speed up to 20 MHz, 33 MHz utilizing two chip select pins.

8.9 Compatibility Module

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently
programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte transfers, and channels
5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be
programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request.
The chipset supports LPC DMA, which is similar to ISA DMA, through the DMA controller. LPC DMA is
handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from
the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the system
timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for
these three counters.
The chipset provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates
the functionality of two, 82C59 interrupt controllers. The two interrupt controllers are cascaded so
that 14 external and two internal interrupts are possible. In addition, the chipset supports a serial
interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save and restore
system state after power has been removed and restored to the platform.

8.10 Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in the
previous section, the Ibex Peak incorporates the Advanced Programmable Interrupt Controller (APIC).
Dell PowerEdge R210 II Technical Guide 33