Hitachi Travelstar 2.5 inch SATA HTS722020K9A300 Oem Specification page 134

Note 1.
When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer
mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode
value.
PIO Default Transfer Mode
PIO Default Transfer Mode, Disable IORDY
PIO Flow Control Transfer Mode x
Multiword DMA mode x
Ultra DMA mode x
When Feature register is 05h (=Enable Advanced Power Management), the Sector Count Register specifies the
Advanced Power Management level.
C0h - FEh ... The deepest Power Saving mode is Active Idle
80h - BFh ... The deepest Power Saving mode is Low power Idle
01h - 7Fh ... The deepest Power Saving mode is Standby
00h, FFh ... Aborted
Note 2.
If the number of auto reassigned sectors reaches the device's reassignment capacity, the write cache
function will be automatically disabled. Although the device still accepts the Set Features
command (with Feature register = 02h) without error, the write cache function will remain disabled.
For current write cache function status, please refer to the Identify Device Information(129word)
by Identify Device command. Power off must not be done in 5 seconds after write command
completion when write cache is enabled.
Note 3.
When Feature register is 85h (=Disable Advanced Power Management), the deepest Power Saving
mode becomes Active Idle.
Note 4.
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the
specific Serial ATA feature to enable or disable.
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the
specific Serial ATA feature to enable or disable.
Sector count value
01h
02h
03h
04h
06h
7K200 SATA OEM Specification
bits
(7:3)
00000
00000
00001
00100
01000
Non-zero buffer offset in DMA setup FIS
DMA setup FIS auto-activate optimization
Device-initiated interface power state transitions
Guaranteed in-order data delivery
Software Settings Preservation
134/173
bits
(2:0)
000
001
nnn (nnn=000,001,010,011,100)
nnn (nnn=000,001,010)
nnn (nnn=000,001,010,011,100,101)
Description