Page 1 Hitachi Global Storage Technologies Hard Disk Drive Specification Hitachi Travelstar 4K120 2.5 inch ATA/IDE hard disk drive Models: HTS421212H9AT00 HTS421210H9AT00 HTS421280H9AT00 HTS421260H9AT00 HTS421240H9AT00 Revision 1.2 12 July 2006...
Page 3 Hitachi Global Storage Technologies Hard Disk Drive Specification Hitachi Travelstar 4K120 2.5 inch ATA/IDE hard disk drive Models: HTS421212H9AT00 HTS421210H9AT00 HTS421280H9AT00 HTS421260H9AT00 HTS421240H9AT00 Revision 1.2 12 July 2006...
Page 4 It is possible that this publication may contain reference to, or information about, Hitachi products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Hitachi intends to announce such Hitachi products, programming, or services in your country.
Page 5: Table Of Contents
Table of Contents 1.0. General............................ 1 1.1. Introduction........................1 1.2. References......................... 1 1.3. Abbreviations........................1 1.4. Caution..........................3 1.5. Drive handling precautions....................4 2.0. Outline of the drive ........................ 5 3.0. Fixed-disk subsystem description..................9 3.1. Control electronics......................9 3.2. Head disk assembly data....................9 4.0.
Page 6 6.3.4 Service life and usage condition ................29 6.3.5 Preventive maintenance ..................29 6.3.6 Load/unload ......................29 6.4. Mechanical specifications....................31 6.4.1 Physical dimensions and weight ................31 6.4.2 Mounting hole locations ..................32 6.4.3 Connector and jumper description ................. 32 6.4.4 Mounting orientation .....................
Page 7 7.9.7 Device Terminating Write DMA ................53 7.9.8 Host Terminating Write DMA ................54 7.10. Drive address setting..................... 55 7.11. Addressing of HDD registers..................56 8.0. General..........................59 8.1. Introduction........................59 8.2. Terminology ........................59 9.0. Deviations from standard....................61 10.0.
Page 8 11.8. S.M.A.R.T. Function ....................76 11.8.1 Attributes ......................77 11.8.2 Attribute values ....................77 11.8.3 Attribute thresholds ..................... 77 11.8.4 Threshold exceeded condition ................77 11.8.5 S.M.A.R.T. commands ..................77 11.8.6 S.M.A.R.T. operation with power management modes ........77 11.9. Security Mode Feature Set.................... 78 11.9.1 Security mode ......................
Page 9 13.12. Read Buffer (E4h)..................... 126 13.13. Read DMA (C8h/C9h)....................127 13.14. Read DMA EXT (25h) ..................... 129 13.15. Read Log Ext (2Fh) ....................131 13.15.1 General purpose log Directory ................ 132 13.15.2 Extended comprehensive SMART error log ........... 133 13.15.3 Error Log version .................... 133 13.15.4 Extended Self-test log sector ................
Page 10 13.46. Write Log Ext (3Fh) ....................197 13.47. Write Long (32h/33h) ....................199 13.48. Write Multiple (C5h) ....................201 13.49. Write Multiple EXT (39h) ..................202 13.50. Write Multiple FUA Ext (CEh) ................204 13.51. Write Sectors (30h/31h).................... 206 13.52. Write Sectors(s) EXT (34h)..................208 13.53.
Page 11 Table of Contents Table 1: Formatted capacities ......................11 Table 2: Data sheet ........................11 Table 3: Cylinder allocation (120GB model format) ..............12 Table 4: Cylinder allocation (100GB model) ................13 Table 5: Cylinder allocation (80GB model format) ..............14 Table 6: Cylinder allocation (60GB model format) ..............15 Table 7: Cylinder allocation (40GB model format) ..............16 Table 8: Performance characteristics ...................17 Table 9: Mechanical positioning performance ................17...
Page 12 Table 43: Drive Address Register ....................65 Table 44: Device Head/Register ....................66 Table 45: Error Register ......................66 Table 46: Status Register ......................67 Table 47: Reset response table ....................69 Table 48: Default Register Values ....................70 Table 49: Diagnostic codes ......................70 Table 50: Device behavior by ATA command ................72 Table 51: Power conditions ......................75 Table 52: Initial setting ........................79 Table 53: Usual operation for POR .....................80...
Page 13 Table 89: Log address definition ....................132 Table 90: Extended comprehensive SMAERT error log ............133 Table 91: Command data structure ....................134 Table 92: Command data structure ....................135 Table 93: Extended Self-test log data structure .................136 Table 94: Extended self-test log descriptor entry ..............137 Table 95: Read Long (22h/23h) ....................138 Table 96: Read Multiple (C4h) ....................140 Table 97: Read Multiple EXT (29h) ..................142...
Page 14 Table 135: Write Buffer (E8h) ....................190 Table 136: Write DMA (CAh/CBh) ..................191 Table 137: Write DMA (35h) ....................193 Table 138: Write Log Ext command ..................197 Table 139: Write Long (32h/33h) ....................199 Table 140: Write Multiple (C5h) ....................201 Table 141: Write Multiple EXT (39h) ..................202 Table 142: Write Multiple FUA Ext (CEh) ................204 Table 143: Write Sectors Command (30h/31h) .................206 Table 144: Write Sector(s) EXT Command (34h) ..............208...
Page 15: General
1.0 General 1.1 Introduction This document describes the specifications of the following Travelstar 4K120, a 2.5-inch hard disk drive, ATA/IDE interface with a rotational speed of 4K120 RPM and a height of 9.5 mm: Drive name Model number Capacity Height (mm) Rotation Speed (rpm) Travelstar 4K120-120...
Page 16 electromagnetic compatibility Error Recovery Procedure Electrostatic Discharge Federal Communications Commission field replacement unit gravity (a unit of force) (32 ft/sec) per Hertz 1,000,000,000 bits 1,000,000,000 bytes ground hexadecimal hard disk drive Hertz Input integrated lead suspension Input/Output International Standards Organization 1,000 bytes Kbpi 1000 bits per inch...
Page 17: Caution
relative humidity % RH per cent relative humidity root mean square revolutions per minute reset read/write second SELV secondary low voltage S.M.A.R.TSelf-Monitoring, Analysis, and Reporting Technology tracks per inch track transistor-transistor logic Underwriters Laboratory volt Verband Deutscher Electrotechniker watt 3-state transistor-transistor tristate logic 1.4 Caution •...
Page 18: Drive Handling Precautions
1.5 Drive handling precautions Do not press on the drive cover during handling. Travelstar 4K120 Hard Disk Drive Specification...
Page 19: Outline Of The Drive
2.0 Outline of the drive • 2.5 inch, 9.5-mm height • Formatted capacities of 120 GB, 100 GB, 80 GB, 60 GB, 40GB • 512 bytes/sector • AT Interface (Enhanced IDE) conforming to ATA/ATAPI-7 • Integrated controller • No-ID recording format •...
Page 20 Travelstar 4K120 Hard Disk Drive Specification...
Page 21 Part 1. Functional specification Travelstar 4K120 Hard Disk Drive Specification...
Page 22 Travelstar 4K120 Hard Disk Drive Specification...
Page 23: Fixed-Disk Subsystem Description
3.0 Fixed-disk subsystem description 3.1 Control electronics The control electronics works with the following functions: • AT Interface Protocol • Embedded Sector Servo • No-ID (TM) formatting • Multizone recording • Code: 100/106 • System ECC • Enhanced Adaptive Battery Life Extender 3.2 Head disk assembly data The following technologies are used in the drive: •...
Page 24 Travelstar 4K120 Hard Disk Drive Specification...
Page 25: Drive Characteristics
4.0 Drive characteristics 4.1 Formatted capacity Table 1: Formatted capacities 120GB 100GB 80GB 60GB 40GB Physical Layout Bytes per sector Sectors per track 504-1008 456-936 476-966 486-1008 432-918 Number of heads Number of disks Logical layout Number of heads Number of Sec- tors/track Number of Cylin- 16,383...
Page 26: Cylinder Allocation
4.3 Cylinder allocation Data format is allocated by each characteristics in 3 different Adaptive formats described below. Table 3: Cylinder allocation (120GB model format) Zone Outer Cylinder Inner Cylinder Sec / Track 7423 1008 7424 11519 11520 16127 16128 18431 18432 22655 22656...
Page 27: Table 4: Cylinder Allocation (100Gb Model)
Table 4: Cylinder allocation (100GB model) Zone Outer Cylinder Inner Cylinder Sec / Track 5567 5568 7771 7772 12875 12876 16007 16008 21111 21112 22039 22040 24939 24940 29463 229464 31667 31668 35495 35496 36887 36888 39439 39440 44311 44312 45355 45356 48023...
Page 28: Table 5: Cylinder Allocation (80Gb Model Format)
Table 5: Cylinder allocation (80GB model format) Zone Outer Cylinder Inner Cylinder Sec / Track 7079 7080 11639 11640 13919 13920 17879 17880 21239 21240 22079 22080 26999 27000 27839 27840 32999 33000 36959 36960 38759 38760 40799 40800 43799 43800 44639 44640...
Page 29: Table 6: Cylinder Allocation (60Gb Model Format)
Table 6: Cylinder allocation (60GB model format) Zone Outer Cylinder Inner Cylinder Sec / Track 7423 1008 7424 11903 11904 18047 18048 19967 19968 23167 23168 25727 25728 29951 29952 33663 33664 35711 35712 39423 39424 41343 41344 43519 43520 45951 45952 50431...
Page 30: Table 7: Cylinder Allocation (40Gb Model Format)
Table 7: Cylinder allocation (40GB model format) Zone Outer Cylinder Inner Cylinder Sec / Track 2841 2842 5291 5292 7251 7252 12151 12152 15581 15582 18815 18816 21755 21756 22539 22540 24793 24794 28517 28518 30085 30086 33319 33320 36357 36358 38317 38318...
Page 31: Performance Characteristics
4.4 Performance characteristics Drive performance is characterized by the following parameters: • Command overhead • Mechanical head positioning Seek time Latency • Data transfer speed • Buffering operation (read ahead/write cache) Note: All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system.
Page 32: Table 10: Full Stroke Seek Time
“Typical” and “Max” are used throughout this document and are defined as follows: Typical Average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions.
Page 33: Operating Modes
4.4.2.4 Average latency Table 12: Average latency Rotational speed Time for one Average latency (RPM) revolution (ms) (ms) 4200 14.3 4.4.2.5 Drive ready time Table 13: Drive ready time Drive ready time (sec) Condition Typical Power on to Ready 3.0 (40, 60GB) 3.5 (80, 100, 120GB) The condition in which the drive is able to perform a media access command (for exam- Ready...
Page 34: Table 15: Drive Ready Time
Table 14: Description of operating modes Operating mode Description The head is unloaded onto the ramp position. The spindle motor is rotating at full Low power idle speed. The device interface is capable of accepting commands. The spindle motor is stopped. Standby All circuitry except the host interface is in power saving mode.
Page 35: Data Integrity
5.0 Data integrity 5.1 Data loss at power off • Data loss will not be caused by a power off during any operation except the write operation. • A power off during a write operation causes the loss of any received or resident data that has not been written onto the disk media.
Page 36: Write Safety
5.4 WRITE safety The drive ensures that the data is written into the disk media properly. The conditions listed below are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked. •...
Page 37: Ecc
5.8 ECC The 10 bit 40 symbol non interleaved ECC processor provides user data verification and correction capa- bility. The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC. The other 34 symbols are Read Solomon ECC. Hardware logic corrects up to 16 symbols (20 bytes) errors on- the-fly.
Page 38 Travelstar 4K120 Hard Disk Drive Specification...
Page 39: Specification
6.0 Specification 6.1 Environment 6.1.1 Temperature and humidity Table 16: Environmental condition Operating conditions Temperature 5 to 55ºC (See note below) Relative humidity 8 to 90%, non-condensing Maximum wet bulb temperature 29.4ºC, non-condensing Maximum temperature gradient 20ºC/hour Altitude –300 to 3,048 m (10,000 ft) Non-operating conditions Temperature –40 to 65ºC...
Page 40: Table 17: Limits Of Temperature And Humidity
Table 17: Limits of temperature and humidity Specification (Environment) 41'C/95% 31'C/90% WetBulb 40'C WetBulb29.4'C Non Operating Operating 65'C/23% 55'C/15% Temperature (degC) Travelstar 4K120 Hard Disk Drive Specification...
Page 41: Radiation Noise
6.1.1.1 Corrosion test The drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50°C/90% RH (relative humidity) for one week followed by a temperature and humidity drop to 25°C/40%RH in 2 hours. 6.1.2 Radiation noise The drive shall work without degradation of the soft error rate under the following magnetic flux density limits at the enclosure surface.
Page 42: Power Consumption Efficiency
Watts (RMS typical) All models Seek average Standby 0.15 Sleep Startup (max. peak) Average from power on to ready Footnotes: The maximum fixed disk ripple is measured at the 5 volt input of the drive. The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of 20 ms) on the 5 volt nominal supply.
Page 43: Cable Noise Interference
6.3.3 Cable noise interference To avoid any degradation of performance throughput or error when the interface cable is routed on top or comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by four screws. The common mode noise or voltage level difference between the system frame and power cable ground or AT interface cable ground should be in the allowable level specified in the power requirement section.
Page 44 HDD to nontypical mechan- ical stress. Power cycling testing may be required to test the boot-up function of the system. In this case Hitachi recommends that the power-off portion of the cycle contain the sequence specified in Section 6.3.6.2, “Required Power-Off Sequence”...
Page 45: Mechanical Specifications
6.4 Mechanical specifications 6.4.1 Physical dimensions and weight The following table lists the dimensions of the drive. Table 21: Physical dimensions and weight 120GB, 100GB, 80GB 60GB, 40GB models models Height [mm] 9.5±0.2 9.5±0.2 Width [mm] 69.85±0.25 69.85±0.25 Length [mm] 100.2±0.25 100.2±0.25 Weight [grams - maximum]...
Page 46: Mounting Hole Locations
6.4.2 Mounting hole locations The mounting hole locations and size of the drive are shown below. 6.4.3 Connector and jumper description A jumper is used to designate the drive address as either master or slave. The jumper setting method is described in Section 7.10, “Drive address setting”...
Page 47: Load/Unload Mechanism
The recommended mounting screw depth is 3.0±0.3 mm for bottom and 3.5±0.5 mm for horizontal mounting. The user is responsible for using the appropriate screws or equivalent mounting hardware to mount the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or spindle rotation. 6.4.5 Load/unload mechanism The head load/unload mechanism is provided to protect the disk data during shipping, movement, or storage.
Page 48: Vibration And Shock
6.5 Vibration and shock All vibration and shock measurements in this section are for drives without mounting attachments for systems. The input level shall be applied to the normal drive mounting points.Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four mounting holes.
Page 49: Nonoperating Vibration
6.5.2 Nonoperating vibration The disk drive withstands the vibration levels described below without any loss or permanent damage. 6.5.2.1 Random vibration The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration of 15 minutes per axis.
Page 50: Acoustics
The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a time. Input levels are measured on a base plate where the drive is attached with four screws 6.6 Acoustics 6.6.1 Sound power levels The criteria of A-weighted sound power level are described below.
Page 51: Discrete Tone Penalty
6.7 Identification labels The following labels are affixed to every drive: • A label which is placed on the top of the head disk assembly containing the statement "Made by Hitachi" or equivalent, part number, EC number, and FRU number.
Page 52: Bsmi Mark
6.8.3 BSMI mark The product complies with the Taiwan EMC standard "Limits and methods of measurement of radio disturbance characteristics of information technology equipment, CNS 13438 Class B." 6.8.4 MIC mark The product complies with the Korea EMC standard. The regulation for certification of information and communi- cation equipment is based on "Telecommunications Basic Act"...
Page 53: Electrical Interface Specification
7.0 Electrical interface specification 7.1 Cabling The maximum cable length from the host system to the hard disk drive plus circuit pattern length in the host system shall not exceed 18 inches. 7.2 Interface connector The signal connector for AT attachment is designed to mate with Dupont part number 69764-044 or equivalent. The figure below and “”...
Page 54: Signal Definitions
7.3 Signal definitions The pin assignments of interface signals are listed as follows:Signal definitions Table 28: Signal definitions SIGNAL Type SIGNAL Type RESET- DD07 3–state DD08 3–state DD06 3–state DD09 3–state DD05 3–state DD10 3–state DD04 3–state DD11 3–state DD03 3–state DD12 3–state...
Page 55: Signal Descriptions
Table 29: SpecMial signal definitions for Ultra DMA Special Definition Conventional (for Ultra DMA) Definition DDMARDY- IORDY Write Operation HSTROBE DIOR- STOP DIOW- HDMARDY- DIOR- Read Operation DSTROBE IORDY STOP DIOW- 7.4 Signal descriptions DD00–DD15 A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Regis- ter and ECC access.
Page 56 DASP- This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is driven by an Open-Drain driver and internally pulled up to 5.0 volts through a 10 k. resistor. During a Power- On initialization or after RESET- is negated, DASP- shall be asserted by device 1 within 400 ms to indicate that device 1 is present.
Page 57 extend the PIO cycle. This line can be connected to the host IORDY signal in order to insert a WAIT state(s) into the host PIO cycle. This signal is an Open-Drain output with 16mA sink capability. 5V Power There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5 V Motor"...
Page 58: Interface Logic Signal Levels
7.5 Interface logic signal levels The interface logic signals have the following electrical specifications: Voltage Input high (ViH) 2.0 V min./5.5 V max. Inputs Voltage input low (ViL) –0.5 V min./0.8 V max. Voltage output high at IoH 2.4 V min. min (VoH) Outputs Voltage output low at IoL...
Page 59: Pio Timings
7.7 PIO timings The PIO cycle timings meet Mode 4 of the ATA/ATAPI-7 description. C S(1:0)- D A(2:0) D IO R -, D IO W - W rite data D D (15:0) R ead data D D (15:0) t7(*) t8(*) IO C S16-(*) IO R D Y (*) U p to ATA-2 (m ode-0,1,2)
Page 60: Multi Word Dma Timings
7.8 Multi word DMA timings The Multi word DMA timings meet Mode 2 of the ATA/ATAPI-7 description. DMARQ tLR/tLW DMACK- tKR/tKW DIOR-/DIOW- READ DD(15:0) WRITE DD(15:0) Table 31: Multiword DMA cycle timings PARAMETER DESCRIPTION MIN (ns) MAX (ns) Cycle time –...
Page 61: Ultra Dma Timings
7.9 Ultra DMA timings The Ultra DMA timings meet Mode 0, 1, 2, 3, 4 and 5 of the Ultra DMA Protocol. 7.9.1 Initiating Read DMA DMARQ DMACK- tACK tENV STOP tACK tENV t2CYC HDMARDY- tZIORDY tCYC tCYC DSTROBE tZAD DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxx...
Page 62: Host Pausing Read Dma
7.9.2 Host Pausing Read DMA DMARQ DMACK- STOP HDMARDY- tRFS DSTROBE Table 33: Ultra DMA cycle timings (Host Pausing Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Page 63: Host Terminating Read Dma
7.9.3 Host Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tRFS tIORDYZ DSTROBE xxx RD Data xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Device drives DD Host drives DD Table 34: Ultra DMA cycle timings (Host Terminating Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4...
Page 64: Device Terminating Read Dma
7.9.4 Device Terminating Read DMA DMARQ tMLI DMACK- tACK STOP tACK HDMARDY- tIORDYZ DSTROBE xxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) tZAH Host drives DD Device drives DD Table 35: Ultra DMA cycle timings (Device Terminating Read) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5...
Page 65: Initiating Write Dma
7.9.5 Initiating Write DMA DMARQ DMACK- tENV tACK STOP tZIORDY t2CYC DDMARDY- tCYC tCYC tACK HSTROBE DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx WT Data WT Data WT Data Host drives DD Table 36: Ultra DMA cycle timing (Initiating Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5...
Page 66: Device Pausing Write Dma
7.9.6 Device Pausing Write DMA DMARQ DMACK- STOP DDMARDY- tRFS HSTROBE Table 37: Ultra DMA cycle timing (Device Pausing Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)
Page 67: Device Terminating Write Dma
7.9.7 Device Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK tRFS HSTROBE xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 38: Ultra DMA cycle timings (Device TerminatingWrite) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER...
Page 68: Host Terminating Write Dma
7.9.8 Host Terminating Write DMA DMARQ tMLI DMACK- tACK STOP tIORDYZ DDMARDY- tACK HSTROBE xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx DD(15:0) Host drives DD Table 39: Ultra DMA cycle timings (Host Terminating Write) MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 PARAMETER DESCRIPTION (ns)
Page 69: Drive Address Setting
7.10 Drive address setting A jumper placed on the interface connector determines the drive address. Three drive addresses are shown below. Two addresses require the setting of a jumper. Setting 1—Device 0 (Master) (no jumper is used) Setting 2—Device 1 (Slave) Setting 3—Cable Select Setting 4—Do not attach a jumper here Setting 5—Do not attach a jumper here...
Page 70: Addressing Of Hdd Registers
7.11 Addressing of HDD registers The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA00–02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time.
Page 71 Part 2. Interface specification Travelstar 4K120 Hard Disk Drive Specification...
Page 72 Travelstar 4K120 Hard Disk Drive Specification...
Page 73: General
8.0 General 8.1 Introduction This specification describes the host interface of the Travelstar 4K120. The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-7) Revision 4b, dated 21 April 2004, with certain limitations described in Section 9.0, “Deviations from standard”...
Page 74 Travelstar 4K120 Hard Disk Drive Specification...
Page 75: Deviations From Standard
9.0 Deviations from standard The device conforms to the referenced specifications, with deviations described below. The interface conforms to the Working Document of Information Technology, AT Attachment with Packet Interface Extension (ATA/ATAPI-7) Revision 4b, dated 21 April 2004, with the following deviation: S.M.A.R.T.
Page 76 Travelstar 4K120 Hard Disk Drive Specification...
Page 77: Register
10.0 Register Table 40: Register Set Addresses Functions CS0- CS1- READ (DIOR-) WRITE (DIOW-) Data bus high impedence Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Device Address Not used Command block registers Data...
Page 78: Alternate Status Register
10.1 Alternate Status Register Table 41: Alternate Status Register This register contains the same information as the Status Register. The only difference between this register and the Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a pending interrupt.
Page 79: Device Control Register
10.4 Device Control Register Table 42: Device Control Register SRST -IEN Definitions HOB (high order byte) is defined by the 48-bit Address feature set. A write to any Command Register shall clear the HOB bit to zero. SRST Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the (RST) device.
Page 80: Device Register
10.6 Device Register Table 44: Device Head/Register This register contains the device and head numbers. Definitions Binary encoded address mode select. When L = 0, addressing is by CHS mode. When L = 1, addressing is by LBA mode. Device. When DRV = 0, device 0 (Master) is selected. When DRV = 1, device 1 (Slave) is selected.
Page 81: Lba High Register
10.9 LBA High Register This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function Set com- mand and Format Unit command. When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 16-23, and the "previous content"...
Page 82 Definitions Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned. DRDY Device Ready.
Page 83: General
11.0 General 11.1 Reset response ATA has the following three types of resets: The device executes a series of electrical circuitry diagnostics, spins up the Power On Reset (POR) head disk assembly, tests speed and other mechanical parametric, and sets default values.
Page 84: Register Initialization
11.2 Register initialization After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below. Table 48: Default Register Values Register Default Value Error Diagnostic Code Sector Count LBA Low LBA Mid LBA High Device...
Page 85: Diagnostic And Reset Considerations
11.3 Diagnostic and Reset considerations The Set Max password, the Set Max security mode and the Set Max unlock counter are not retained over a Power On Reset but are retained over a Hard Reset or Soft Reset. For each Reset and Execute Device Diagnostic, the diagnostic is done as follows: Power On DASP–...
Page 86: Power-Off Considerations
11.4 Power-off considerations 11.4.1 Load/Unload Load/Unload is a functional mechanism of the hard disk drive and is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the following commands. Table 50: Device behavior by ATA command Command Response Standby...
Page 87: Sector Addressing Mode
You may then turn off the drive in the following order: 1. Issue Standby Immediate or sleep command 2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in a typical case.) 3. Terminate power to drive This power-down sequence should be followed for entry into any system power-down state, system suspend state, or system hibernation state.
Page 88: Power Management Features
11.6 Power management features The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.
Page 89: Standby Timer
11.6.4 Standby timer The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the standby mode.
Page 90: Performance Idle Mode
• A SET FEATURES subcommand to enable Advanced Power Management • A SET FEATURES subcommand to disable Advanced Power Management The Advanced Power Management feature is independent of the Standby timer setting. If both Advanced Power Management level and the Standby timer are set, the device will go to the Standby state when the timer times out or the device's Advanced Power Management algorithm indicates that it is time to enter the Standby state.
Page 91: Attributes
system of a negative reliability status condition, the host system can warn the user of the impending risk of a data loss and advise the user of appropriate action. Since S.M.A.R.T. utilizes the internal device microprocessor and other device resources, there may be some small overhead associated with its operation.
Page 92: Security Mode Feature Set
the attribute auto save feature when it utilizes the power management. If the attribute auto save feature is enabled, attribute values will be saved after 30 minutes have passed since the last saving, besides above condition. 11.9 Security Mode Feature Set Security Mode Feature Set is a powerful security feature.
Page 93: Master Password Revision Code
The system manufacturer or dealer who intends to enable the device lock function for end users must set the master password even if only single level password protection is required. Otherwise, the default master password which is set by Hitachi Global Storage Technologies can unlock a device that is locked with a user password 11.9.4 Master Password Revision Code This Master Password Revision Code is set by Security Set Password command with the master password.
Page 94: Table 53: Usual Operation For Por
11.9.4.3 Operation from POR after user password is set When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command is successfully completed. Table 53: Usual operation for POR Device Locked mode Unlock CMD Erase Prepare Non-media Access Media Access...
Page 95: Table 54: Password Lost
11.9.4.4 User Password lost If the User Password is forgotten and High level security is set, the system user cannot access any data. However the device can be unlocked using the Master Password. If a system user forgets the User Password and Maximum security level is set, data access is impossible. However the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with the Master Password.
Page 96: Command Table
11.9.5 Command table This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is enabled. Table 55: Command table for device lock operation Device Mode Device Mode Command Command Locked Unlocked Frozen Locked Unlocked Frozen Check Power Mode...
Page 97: Protected Area Function
11.10 Protected Area Function Protected Area Function provides a protected area which cannot be accessed via conventional methods. This protected area is used to contain critical system data such as BIOS or system management information. The contents of the entire system main memory may also be dumped into the protected area to resume after a system power off. The LBA/CYL changed by the following commands affects the Identify Device Information.
Page 98: Set Max Security Extension Commands
From this point the protected area cannot be accessed until the next Set Max ADDRESS command is issued. Any BIOS, device driver, or application software accesses the drive as if it is a 528 MB device because the device behaves like a 528 MB device. 3.
Page 99: Address Offset Feature (Vendor Specific)
The password, the Set Max security mode, and the unlock counter do not persist over a power cycle but persist over a hardware or software reset. NOTE: If this command is immediately preceded by a Read Native MAX ADDRESS command, it shall be interpreted as a Set Max ADDRESS command regardless of Feature register value.
Page 100: Identify Device Data
Disable Address Offset Feature removes the address offset and sets the size of the drive reported by the Identify Device command back to the size specified in the last nonvolatile Set Max Address command. Table 58: Device address map before and after Set Feature 11.11.2 Identify Device Data Identify Device data, word 83, bit 7 indicates the device supports the Address Offset Feature.
Page 101: Seek Overlap
11.12 Seek Overlap The drive provides accurate seek time measurement method. The seek command is usually used to measure the device seek time by accumulating execution time for a number of seek commands. With typical implementation of the seek command, this measurement must include the device and host command overhead. To eliminate this overhead, the drive overlaps the seek command as described below.
Page 102: Reassign Function
11.14 Reassign Function The Reassign Function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. The one entry can register 256 consecutive sectors maximum. This reassignment information is registered internally, and the information is available right after completing the reassign function.
Page 103: 48-Bit Address Feature Set
11.15 48-bit Address Feature Set The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred by a single command are increased by increasing the allowable sector count to 16 bits. Commands unique to the 48-bit Address feature set are: •...
Page 104 Travelstar 4K120 Hard Disk Drive Specification...
Page 105: Command Protocol
12.0 Command protocol The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check to see if BSY = 1, and should proceed no further unless and until BSY = 0.
Page 106: Data Out Commands
f. The device sets DRQ = 0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY = 1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets BSY = 0 and DRQ=1 and interrupts the host.
Page 107: Non-Data Commands
• Write Multiple FUA EXT • Write Sector(s) • Write Sector(s) EXT • Write Verify Execution includes the transfer of one or more 512 byte (> 512 bytes on Write Long) sectors of data from the host to the device. 1.
Page 108 • Flush Cache • Flush Cache EXT • Format Unit • Idle • Idle Immediate • Initialize Device Parameters • Read Native Max ADDRESS • Read Native Max ADDRESS EXT • Read Verify Sector(s) • Read Verify Sector(s) EXT • Recalibrate •...
Page 109: Dma Data Transfer Commands
12.4 DMA Data Transfer commands: The following are DMA Data Transfer commands: • Read DMA • Read DMA EXT • Write DMA • Write DMA EXT • Write DMA FUA EXT Data transfers using DMA commands differ in two ways from PIO transfers: •...
Page 110 Travelstar 4K120 Hard Disk Drive Specification...
Page 111: Command Descriptions
13.0 Command descriptions The table below shows the commands that are supported by the device. Table 62: “Command Set (subcommand)” on page 101 shows the subcommands that are supported by each command or feature. Table 60: Command Set (1 of 2) Code Binary Code Bit Protocol...
Page 112 Seek 0 1 1 1 - - - - Sense Condition 1 1 1 1 0 0 0 0 Travelstar 4K120 Hard Disk Drive Specification...
Page 113 Table 61: Command Set (2 of 2) Binary Code Bit Proto- Code Command (Hex) 7 6 5 4 3 2 1 0 Set Features 1 1 1 0 1 1 1 1 Set Max ADDRESS 1 1 1 1 1 0 0 1 Set Max ADDRESS EXT 0 0 1 1 0 1 1 1 Set Max FREEZE LOCK...
Page 114 Protocol: 1 : PIO data IN command 3 : Non data command + : Vendor specific command 2 : PIO data OUT command 4 : DMA command Travelstar 4K120 Hard Disk Drive Specification...
Page 115: Table 62: Command Set (Subcommand)
Table 62: Command Set (subcommand) Command Feature Command (Subcommand) Code (Hex) Register (Hex) S.M.A.R.T. Function S.M.A.R.T. Read Attribute Values S.M.A.R.T. Read Attribute Thresholds S.M.A.R.T. Enable/Disable Attribute Autosave S.M.A.R.T. Save Attribute Values S.M.A.R.T. Execute Off-line Immediate S.M.A.R.T. Read Log Sector S.M.A.R.T. Write Log Sector S.M.A.R.T.
Page 116 The "Command set" table beginning on page page 97 shows the commands that are supported by the device. The "Command Set (Subcommand)" table above shows the sub-commands that are supported by each command or fea- ture. The following symbols are used in the command descriptions: Input registers This indicates that the bit is always set to 0.
Page 117: Check Power Mode (E5H/98H)
13.1 Check Power Mode (E5h/98h) Table 63: Check Power Mode Command (E5h/98h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 118: Device Configuration Overlay (B1H)
13.2 Device Configuration Overlay (B1h) Table 64: Device Configuration Overlay Command (B1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 119: Device Configuration Identify (Subcommand C2H)
13.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO data-in transfer. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.
Page 120: Table 66: Device Configuration Overlay Data Structure
Table 66: Device Configuration Overlay Data structure Word Content 0001h Data Structure revision Multiword DMA modes supported 15-3 Reserved 1 = Multiword DMA mode 2 and below are supported 1 = Multiword DMA mode 1 and below are supported 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported 15-6 Reserved...
Page 121: Execute Device Diagnostic (90H)
13.3 Execute Device Diagnostic (90h) Table 68: Execute Device Diagnostic command (90h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 122: Flush Cache (E7H)
13.4 Flush Cache (E7h) Table 69: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 123: Flush Cache Ext (Eah)
13.5 Flush Cache EXT (EAh) Table 70: Flush Cache command (E7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 124: Format Track (50H: Vendor Specific)
13.6 Format Track (50h: vendor specific) Table 71: Format Track command (50h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 125: Format Unit (F7H: Vendor Specific)
13.7 Format Unit (F7h: vendor specific) Table 72: Format Unit command (F7h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 126: Identify Device (Ech)
13.8 Identify Device (ECh) Table 73: Identify Device command (ECh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 127 Table 74: Identify device information. (Part 1 of 7) Word Content Description 045xH drive classi- bit assignments fication 15(=0) 1=ATAPI device, 0=ATA device 14(=0) 1=format speed tolerance gap required 13(=0) 1=track offset option available 12(=0) 1=data strobe offset option available 11(=0) 1=rotational speed tolerance >...
Page 128 Table 75: Identify device information. (Part 2 of 7) Word Content Description 0000H * Capable of double word I/O, '0000'= cannot perform 0F00H Capabilities, bit assignments: 15-14(=0) Reserved 13(=0) 0= Standby timer value are vendor specific 12(=0) Reserved 11(=1) 1= IORDY Supported 10(=1) 1= IORDY can be disabled 9(=1)
Page 129 * indicates the use of those parameters that are vendor specific. Note 1. See Table 81: “Number of cylinders/heads/sectors by model.” on page 122. Table 76: Identify device information. (Part 3 of 7) Word Content Description 0003H Flow Control PIO Transfer Modes Supported 15- 8(=0) Reserved 7- 0(=3)
Page 130 Table 77: Identify device information. (Part 4 of 7) Word Content Description 7FE9H Command set supported 15(=0) Always 14(=1) Always 13(=1) 1=FLUSH CACEH EXT command supported 12(=1) 1=FLUSH CACHE command supported 11(=1) 1=Device Configuration Overlay command supported 10(=1) 1=48-bit Address feature set supported 9(=1) 1=Automatic Acoustic Management supported ** 8(=1)
Page 131 74XXH Command set/feature enabled 15(=0) Obsolete 14(=1) 1=NOP command supported 13(=1) 1=READ BUFFER command supported 12(=1) 1=WRITE BUFFER command supported 11(=0) Reserved **10(=1) 1=Host Protected Area Feature Set supported 9(=0) 1=DEVICE RESET command supported 8(=0) 1=SERVICE interrupt enabled 7(=0) 1=release interrupt enabled 6(=X) 1=look-ahead enabled 5(=X)
Page 132: Table 78: Identify Device Information. (Part 5 Of 7
Table 78: Identify device information. (Part 5 of 7 Word Content Description 3XXXH Command set/feature enabled 15-14(=0) Reserved 13(=1) 1=FLUSH CACHE EXT command supported 12(=1) 1=FLUSH CACHE command supported 11(=x) 1=Device Configuration Overlay supported 10(=1) 1=48-bit Address feature set supported 9(=X) 1=Automatic Acoustic Management enabled 8(=X)
Page 133 XX3FH Ultra DMA Transfer mode (mode 5 supported) 15(=0) Reserved 14(=0) 1=UltraDMA mode 6 is selected 13(=X) 1=UltraDMA mode 5 is selected 12(=X) 1=UltraDMA mode 4 is selected 11(=X) 1=UltraDMA mode 3 is selected 10(=X) 1=UltraDMA mode 2 is selected 9(=X) 1=UltraDMA mode 1 is selected 8(=X)
Page 134 Table 79: Identify device information. (Part 6 of 7) Word Content Description 40XXH Current Advanced Power Management level 15- 8(=40h) Reserved 7- 0(=xxh) Current Advanced Power Management level set by Set Features Command (01h to FEh) XXXXH Current Master Password Revision Codes XXXXH Hardware reset results 15-13...
Page 135 Table 80: Identify device information. (Part 7 of 7) Word Content Description 108- XXXX World Wide Name 112- 0000H * Reserved 0000H * Removable Media Status Notification feature set 0xxxH * Security status. Bit assignments Ultra DMA Transfer mode (mode 5 supported) 15-9(=0) Reserved 8(=X)
Page 136: Table 81: Number Of Cylinders/Heads/Sectors By Model
Table 81: Number of cylinders/heads/sectors by model. Microcode revision MBx0Axxx HTS421212H9AT00 Number of cylinders 3FFFh Number of heads Buffer size 3AED1h Total number of user DF94BB0h addressable sectors HTS421210H9AT00 Number of cylinders 3FFFh Number of heads Buffer size 3AD1h Total number of user BA52230h addressable sectors HTS421280H9AT00...
Page 137: Idle (E3H/97H)
13.9 Idle (E3h/97h) Table 82: Idle command (E3h/97h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 138: Idle Immediate (E1H/95H)
13.10 Idle Immediate (E1h/95h) Table 83: Idle Immediate command (E1h/95h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 139: Initialize Device Parameters (91H)
13.11 Initialize Device Parameters (91h) Table 84: Initialize Device Parameters command (91h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 140: Read Buffer (E4H)
13.12 Read Buffer (E4h) Table 85: Read Buffer (E4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 141: Read Dma (C8H/C9H)
13.13 Read DMA (C8h/C9h) Table 86: Read DMA command (C8h/C9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 142 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs. LBA Low This indicates the sector number of the last transferred sector. (L = 0). In LBA mode this register contains the current LBA bits 0–7.
Page 143: Read Dma Ext (25H)
13.14 Read DMA EXT (25h) Table 87: Read DMA EXT (25h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 144 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 145: Read Log Ext (2Fh)
13.15 Read Log Ext (2Fh) Table 88: Read Log Ext command (2Fh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 146: General Purpose Log Directory
Table 89: Log address definition The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit entries contained in the SMART self-test log sector shall also be included in the Comprehensive SMART self-test log sector with the 48-bit entries.
Page 147: Extended Comprehensive Smart Error Log
13.15.2 Extended comprehensive SMART error log defines the format of each of the sectors that comprise the Extended Comprehensive SMART error log. Error log data structure shall not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or in valid addresses.
Page 148: Table 91: Command Data Structure
Command data structure: Data format of each command data structure is shown below. Table 91: Command data structure Description Bytes Offset Device Control register Features register (7:0) (see Note) Features register (15:8) Sector count register (7:0) Sector count register (15:8) Sector number register (7:0) Sector number register (15:8) Cylinder Low register (7:0)
Page 149: Table 92: Command Data Structure
Table 92: Command data structure State shall contain a value indicating the state of the device when the command was issued to the device or the reset occurred as described below. Value State Value State Unknown Sleep Standby Active/Idle SMART Off-line or Self-test x5h-xAh Reserved...
Page 150: Extended Self-Test Log Sector
13.15.3.3 Device error count This field shall contain the total number of errors attributable to the device that have been reported by the device during the life of the device. This count shall not include errors attributed to the receipt of faulty commands such as commands codes not implemented by the device or requests with invalid parameters or invalid addresses.
Page 151: Table 94: Extended Self-Test Log Descriptor Entry
Table 94: Extended self-test log descriptor entry Description Bytes Offset Self-test number Self-test execution status Power-on life timestamp in hours Self-test failure check point Failing LBA (7:0) Failing LBA (15:8) Failing LBA (23:16) Failing LBA (31:24) Failing LBA (39:32) Failing LBA (47:40) Vendor specific Travelstar 4K120 Hard Disk Drive Specification...
Page 152: Read Long (22H/23H)
13.16 Read Long (22h/23h) Table 95: Read Long (22h/23h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 153 LBA Low This indicates the sector number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 0–7. (L = 1) LBA High/Mid This indicates the cylinder number of the transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Low), 16–23 (High).
Page 154: Read Multiple (C4H)
13.17 Read Multiple (C4h) Table 96: Read Multiple (C4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 155 LBA High/Mid This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 8–15 (Mid), 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode, this register contains current LBA bits 24–27.
Page 156: Read Multiple Ext (29H)
13.18 Read Multiple EXT (29h) Table 97: Read Multiple EXT (29h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 157: Read Native Max Address (F8H)
13.19 Read Native Max ADDRESS (F8h) Table 98: Read Native Max ADDRESS (F8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 158: Read Native Max Address Ext (27H)
13.20 Read Native Max ADDRESS EXT (27h) Table 99: Read Native Max ADDRESS EXT (27h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 159: Read Sectors (20H/21H)
13.21 Read Sectors (20h/21h) Table 100: Read Sectors (20h/21h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 160: Read Sector(S) Ext (24H)
13.22 Read Sector(s) EXT (24h) Table 101: Read Sector(s) EXT Command (24h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 161 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 162: Read Verify Sectors (40H/41H)
13.23 Read Verify Sectors (40h/41h) Table 102: Read Verify Sectors (40h/41h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 163 LBA High/Mid This is the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This is the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 164: Ready Verify Sector(S) Ext (42H)
13.24 Ready Verify Sector(s) EXT (42h) Table 103: Read Verify Sector(s) EXT Command (42h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 165 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 166: Recalibrate (1Xh)
13.25 Recalibrate (1xh) Table 104: Recalibrate (1xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 167: Security Disable Password (F6H)
13.26 Security Disable Password (F6h) Table 105: Security Disable Password (F6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 168: Security Erase Prepare (F3H)
13.27 Security Erase Prepare (F3h) Table 107: Security Erase Prepare Command (F3h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 169: Security Erase Unit (F4H)
13.28 Security Erase Unit (F4h) Table 108: Security Erase Unit (F4h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 170 This command disables the security mode feature (device lock function), however, the master password is still stored internally within the device and may be reactivated later when a new user password is set. If you execute this command on disabling the security mode feature (device lock function), the password sent by the host is NOT compared with the Master Password and the User Password.
Page 171: Security Freeze Lock (F5H)
13.29 Security Freeze Lock (F5h) Table 110: Security Freeze Lock (F5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 172: Security Set Password (F1H)
13.30 Security Set Password (F1h) Table 111: Security Set Password (F1h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 173 Security Level A zero indicates a High level, a one indicates a Maximum level. If the host sets the High level and the password is forgotten then the Master Password can be used to unlock the device. If the host sets the Maximum level and the user password is forgotten, only a Security Erase Prepare/Security Unit command can unlock the device and all data will be lost.
Page 174: Security Unlock (F2H)
13.31 Security Unlock (F2h) Table 113: Security Unlock (F2h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 175: Seek (7Xh)
13.32 Seek (7xh) Table 114: Seek (7xh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 176: Sense Condition (F0H: Vendor Specific)
13.33 Sense Condition (F0h: vendor specific) Table 115: Sense Condition (F0h: vendor specific) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - -...
Page 177: Set Features (Efh)
13.34 Set Features (EFh) Table 116: Set Features (EFh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 178 Disable Power-Up in Standby feature set Disable Address Offset mode 4 bytes of ECC apply on Read Long/Write Long commands Enable read look-ahead feature Disable Automatic Acoustic Management feature set Enable reverting to power on defaults Note 1. When the Feature register is 03h (= Set Transfer mode) the Sector Count Register specifies the transfer mechanism.
Page 179: Set Max Address (F9H)
13.35 Set Max ADDRESS (F9h) Table 117: Set Max ADDRESS (F9h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 180 If a host protected area has been established by a Set Max Address Ext command, the device shall return command aborted Output parameters to the device Feature Destination code for this command SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK When the Set Max ADDRESS command is executed, this register is ignored.
Page 181: Set Max Address Ext (37H)
13.36 Set Max ADDRESS EXT (37h) Table 118: Set Max ADDRESS EXT Command (37h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low...
Page 182 Output parameters to the device Option bit for selection whether nonvolatile or volatile. B=0 is volatile condition. When B=1, MAX Address which is set by Set Max Address Ext command is preserved by POR. When B=0, MAX Address which is set by Set Max Address Ext command will be lost by POR.
Page 183: Set Multiple (C6H)
13.37 Set Multiple (C6h) Table 119: Set Multiple command (C6h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 184: Sleep (E6H/99H)
13.38 Sleep (E6h/99h) Table 120: Sleep (E6h/99h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 185: Function Set (B0H)
13.39 S.M.A.R.T. Function Set (B0h) Table 121: S.M.A.R.T. Function Set (B0h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 186 A value of 00h—written by the host into the device's Sector Count Register before issuing the S.M.A.R.T. Enable/ Disable Attribute Autosave subcommand—will cause this feature to be disabled. Disabling this feature does not preclude the device from saving Attribute Values to the Attribute Data sectors during some other normal operation such as during a power-up or a power-down.
Page 187: Table 122: Selective Self-Test Span Example
Self-test execution status byte (see Table 123: “Device Attribute Data Structure” on page 177) and ATA registers and then executes the command completion. See definitions below. Status Set ERR to one when the self-test has failed Error Set ABRT to one when the self-test has failed LBA Low Set to F4h when the self-test has failed LBA High...
Page 188 Instead error locations may be logged for future reallocation. If the device is powered-down before the off-line scan is completed, the off-line scan shall resume when the device is again powered up. From power-up, the resumption of the scan shall be delayed the time indicated in the Selective self-test pending time field in the Selective self-test log.
Page 189 Attribute Values will no longer be monitored. The state of S.M.A.R.T.—either enabled or disabled—is preserved by the device across power cycles. Note that this subcommand does not preclude the device's power mode attribute auto saving. Upon receipt of the S.M.A.R.T. Disable Operations subcommand from the host, the device asserts BSY, disables S.M.A.R.T.
Page 190 the off-line data collection activities which is initiated by the S.M.A.R.T. Execute Off-line Immediate (Subcom- mand D4h) or automatically if the off-line read scanning feature is disabled. A value of F8h written by the host into the device's Sector Count register before issuing this subcommand shall cause the automatic Off-line data collection feature to be enabled.
Page 191: Device Attribute Data Structure
13.39.2 Device Attribute Data Structure The following defines the 512 bytes that make up the Attribute Value information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand. All multibyte fields shown in these data structures follow the ATA/ATAPI-7 specification for byte ordering, namely, that the least significant byte occupies the lowest numbered byte address location in the field.
Page 192: Individual Attribute Data Structure
13.39.2.2 Individual Attribute Data Structure The following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure. Description Byte Offset Value Attribute ID Number (01h to FFh) binary Status Flags bit flags Bit 0 Pre-Failure/Advisory Bit 1...
Page 193: Table 124: Status Flag Definitions
Table 124: Status Flag definitions Flag Name Definition Pre-Failure/ If bit = 0, an Attribute Value less than or equal to its Advisory bit corresponding Attribute Threshold indicates an Advisory condition where the usage or age of the device has exceeded its intended design life period.
Page 194 13.39.2.4 Self-test execution status Definition Percent Self-test remaining. An approximation of the percent of the self-test routine remaining until completion given in ten percent increments. Valid values are 0 through 9. Current Self-test execution status. 0 The self-test routine completed without error or has never been run. 1 The self-test routine was aborted by the host.
Page 195 Off-line Read Scanning implemented bit The device does not support Off-line Read Scanning The device supports Off-line Read Scanning Self-test implemented bit Self-test routing is not implemented Self-test routine is implemented Reserved (0) 13.39.2.8 S.M.A.R.T. Capability This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h indicating that the device will save its Attribute Values prior to going into a power saving mode and supports the S.M.A.R.T.
Page 196: Device Attribute Thresholds Data Structure
13.39.3 Device Attribute Thresholds data structure The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All multibyte fields shown in these data structures follow the ATA/ATAPI-7 specification for byte ordering, that is, that the least significant byte occupies the lowest numbered byte address location in the field.
Page 197: Log Directory
13.39.4 S.M.A.R.T Log Directory Table 126 defines the 512 bytes that make up the S.M.A.R.T Log Directory. The S.M.A.R.T Log Directory is on S.M.A.R.T Log Address zero and is defined as one sector long. Table 126: S.M.A.R.T. Log Director Description Offset Bytes S.M.A.R.T.
Page 198: Table 127: Command Data Structure
13.39.5.3 Device error count This field contains the total number of errors. The value will not roll over. 13.39.5.4 Error log data structure The data format of each error log structure is shown below. Table 127: Command data structure. Description Byte Offset 1st command data structure...
Page 199: Self-Test Log Data Structure
State field contains a value indicating the device state when command was issued to the device. Value State Unknown Sleep Standby Active/Idle S.M.A.R.T. Off-line or Self-test x5h-xAh Reserved xBh-xFh Vendor specific Note: The value of x is vendor specific 13.39.6 Self-test log data structure The following defines the 512 bytes that make up the Self-test log sector.
Page 200: Table 131: Selective Self-Test Log
Table 131: Selective self-test log Travelstar 4K120 Hard Disk Drive Specification...
Page 201: Error Reporting
13.39.8 Error reporting The following table shows the values returned in the Status and Error Registers when specific error conditions are encountered by a device. Table 132: S.M.A.R.T. Error Codes Error condition Status Register Error Register A S.M.A.R.T. FUNCTION SET command was received by the device without the required key being loaded into the LBA High and LBA Mid registers.
Page 202: Standby (E2H/96H)
13.40 Standby (E2h/96h) Table 133: Standby (E2h/96h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 203: Standby Immediate (E0H/94H)
13.41 Standby Immediate (E0h/94h) Table 134: Standby Immediate (E0h/94h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 204: Write Buffer (E8H)
13.42 Write Buffer (E8h) Table 135: Write Buffer (E8h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 205: Write Dma (Cah/Cbh)
13.43 Write DMA (CAh/CBh) Table 136: Write DMA (CAh/CBh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 206 LBA Low This indicates the sector number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 0–7. (L = 1) LBA High/Mid This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High).
Page 207: Write Dma Ext (35H)
13.44 Write DMA EXT (35h) Table 137: Write DMA (35h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 208 LBA High Current LBA (23-16) LBA High Previous LBA (47-40) Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1)
Page 209: Write Dma Fua Ext (3Dh)
13.45 Write DMA FUA Ext (3Dh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 210 LBA High Current LBA (23-16) LBA High Previous LBA (47-40) Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1)
Page 211: Write Log Ext (3Fh)
13.46 Write Log Ext (3Fh) Table 138: Write Log Ext command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 212 Travelstar 4K120 Hard Disk Drive Specification...
Page 213: Write Long (32H/33H)
13.47 Write Long (32h/33h) Table 139: Write Long (32h/33h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 214 LBA High/Mid This indicates the cylinder number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This indicates the head number of the sector to be transferred. (L = 0) In LBA mode this register contains current the LBA bits 24–27.
Page 215: Write Multiple (C5H)
13.48 Write Multiple (C5h) Table 140: Write Multiple (C5h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 216: Write Multiple Ext (39H)
13.49 Write Multiple EXT (39h) Table 141: Write Multiple EXT (39h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - - Data High...
Page 217 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 218: Write Multiple Fua Ext (Ceh)
13.50 Write Multiple FUA Ext (CEh) Table 142: Write Multiple FUA Ext (CEh) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 219 Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 220: Write Sectors (30H/31H)
13.51 Write Sectors (30h/31h) Table 143: Write Sectors Command (30h/31h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data - - - - - - - - Data - - - - - - - - Feature...
Page 221 LBA High/Mid This indicates the cylinder number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 8–15 (Mid) and bits 16–23 (High). (L = 1) This indicates the head number of the last transferred sector. (L = 0) In LBA mode this register contains the current LBA bits 24–27.
Page 222: Write Sectors(S) Ext (34H)
13.52 Write Sectors(s) EXT (34h) Table 144: Write Sector(s) EXT Command (34h) Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low - - - - - - - - Data Low - - - - - - - -...
Page 223: Write Verify (3Ch: Vendor Specific)
Input parameters from the device LBA Low (HOB=0) LBA (7-0) of the address of the first unrecoverable error LBA Low (HOB=1) LBA (31-24) of the address of the first unrecoverable error LBA Mid (HOB=0) LBA (15-8) of the address of the first unrecoverable error LBA Mid (HOB=1) LBA (39-32) of the address of the first unrecoverable error LBA High (HOB=0)
Page 224 Travelstar 4K120 Hard Disk Drive Specification...
Page 225: Timings
14.0 Timings The timing of BSY and DRQ in Status Register are shown in the table below. Table 145: Time-out values INTERVAL START STOP TIME-OUT Power On Device Busy After Power On Status Register BSY=1 400 ns Power On Device Ready After Power On Status Register BSY=0 31 sec...
Page 226 Note 1. For SECURITY ERASE UNIT command, the execution time is referred to 13.28, “Security Erase Unit (F4h)” on page 155. Note 2. For FORMAT UNIT command, the execution time is referred to 13.7, “Format Unit (F7h: vendor specific)” on page 111. Travelstar 4K120 Hard Disk Drive Specification...
Page 227: Appendix
15.0 Appendix 15.1 Commands Support Coverage The table below compares the command support coverage of the Travelstar 4K120 with the ATA-7 defined command set. The third column indicates the capability of the Travelstar 4K120 for those commands. Table 146: Command coverage (1 of 2) Implementation for ATA-7 Category Code...
Page 228 Table 146: Command coverage (1 of 2) Implementation for ATA-7 Category Code Command Name Travelstar 4K120 Type READ DMA QUEUED Optional Table 147: Command coverage (2 of 2) Implementation for ATA-7 Category Code Command Name Travelstar 4K120 Type READ DMA Mandatory READ DMA Obsoleted...
Page 229: Set Features Commands Support Coverage
Table 147: Command coverage (2 of 2) Implementation for ATA-7 Category Code Command Name Travelstar 4K120 Type Reserved: all remaining codes Reserved Reserved Note 1. These commands have two command codes and appear in this table twice, once for each command code.
Page 230 Table 148: SET FEATURES command coverage Features Implementation for Features Name Register Travelstar 4K120 Enable Media Status Notification Enable read look-ahead feature Set 4 bytes ECC Disable Automatic Acoustic Management Enable reverting to power on defaults Disable release interrupt Disable SERVICE interrupt others Reserved Reserved...
Page 231: Changes From The Travelstar 5K100
15.3 Changes from the Travelstar 5K100 The changes between the Travelstar 5K100 and the Travelstar 4K120 are listed below: • Identify device information data Travelstar 4K120 Hard Disk Drive Specification...
Page 232 Travelstar 4K120 Hard Disk Drive Specification...
Page 233 Index Acoustics 36 Address Feature Set 89 Address Offset Feature 85 Advanced Power Management (ABLE-3) feature 75 Appendix 213 BSMI mark 37 Cable noise interference 29 Capacity, formatted 11 CE mark 37 Check Power Mode 103 Command descriptions 97 Command overhead 17 Command protocol 91 Command table 82 Commands Support Coverage 213...
Page 234 DC power requirements 27 Deviations from standard 61 Device Configuration Overlay 104 Device Control Register 65 Discrete tone penalty 37 Drive Address Register 65 Drive address setting 55 Drive characteristics 11 Drive handling precautions 4 Drive ready time 19 Electrical interface specification 39 Electromagnetic compatibility 37 Emergency unload 30 Environment 25...
Page 235 Interface connector 39 Labels, Identification 37 Latency, average 19 LBA High Register 67 LBA Mid Register 67 Load/unload 29 Mechanical positioning 17 Mechanical specifications 31 Mode transition time 20 Mounting hole locations 32 Mounting orientation 32 Non-data commands 93 Operating modes description 19 Packaging 38 Performance characteristics 17...
Page 236 Radiation noise 27 Read Buffer 126 Read DMA 127 Read DMA EXT 129 Read Long 134 Read Native Max ADDRESS 143 Read Sectors 145 Read Verify Sectors 148 Recalibrate 152 Register 63 Register initialization 70 Register set 63 Reset response 69 Reset timings 44 S 171 S.M.A.R.T.
Page 237 Sound power levels 36 Specification 25 Standby 188 Standby timer 75 Status 75 Status Register 67 Temperature 25 Time-out values 211 Transition time 76 UL approval 38 Vibration 34 Write Buffer 190 Write Cache function 87...
Page 239 References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information pur- poses only and does not constitute a warranty.

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Hitachi HTS421212H9AT00 - Travelstar 120 GB Hard Drive Specifications

General

Outline of the Drive

Fixed-Disk Subsystem Description

Drive Characteristics

Data Integrity

Specification

Electrical Interface Specification

General

Deviations from Standard

Register

General

Command Protocol

Command Descriptions

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