Oki C9500dxn Maintenance Manual page 18

(1) CPU
The CPU is 64-bit bus RISC processor PowerPC750CXe, which receives an input of 100MHz
(=BUS CLK) and operates at 450MHz or 600MHz.
(2) Secondary Cache SRAM
PowerPC750Cxe has its cache only inside of it.
Speed:
Capacity:
Primary Cache:
Secondary Cache: 256 K bytes
(3) ROM
The ROM is inserted into the two 168th-pin DIMM slots. The slot A is for a program ROM and
the slot B is for the Japanese Kanji font.
(4) RAM
The RAM is inserted into the three 168th-pin DIMM slots.
SDRAM DIMM Specifications:
Speed:
Capacity:
Configuration: Without parity and ECC. Requires the SPD information.
(5) EEPROM
The EEPROM, an 8-pin DIP package, is inserted into the IC socket and of 16 kilobits for 3.3V
power supply. Settings for controlling the controller block are stored in the memory.
(6) Flash ROM
A 4MB flash ROM is surface-mounted on the TIG board. The flash ROM can store fonts and
macros.
(7) Memory Control LSI (CAI)
A 696-pin BGA package ASIC made by NEC. The chip mainly controls a CPU I/F, memory,
video data compression and decompression, and PU-video I/F.
(8) Interface Control LSI (C2)
A BGA package ASIC made by Toshiba, which controls a PU command I/F, operator panel
I/F, IDE I/F, Centronics I/F, USB I/F, PCI I/F, EEPROM and SPD (SDRAM DIMM) I/F.
(9) IDE HDD
An IDE connector is surface-mounted on the board to which an IDE HDD assembled using
molds for the purpose is connected. The IDE HDD is used for storing font data, spooling
edited video data temporarily and registering form data.
(10) PCI Bus Option
Two PCI I/F slots are provided for option board use. The bus, which uses an Oki Data original
connector, can accept an Ethernet board.
(11) Host Interface
Standard:
Additional Board: (connected to PCI BUS)
41956001TH Rev.1
Same as CPU Core CLK speed
32 K bytes in D-cache capacity, 32 K bytes in I-cache capacity
PC133 or more
64/128/256/512MB
Centronics two-way parallel I/F (IEEE-1284-compliant)
USG (USB1.1-compliant)
Ethernet Board
Oki Data CONFIDENTIAL
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